SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
SiI-DS-0103-D
84
2007 Silicon Image, Inc.
If enabled, a PMACK will be sent to the device; if not enabled, a PMNAK will be sent. When the request is
received and its acknowledgement is enabled, Slumber mode is entered.
Slumber mode status is reported in both the SStatus register (‘0110’ in the IPM field) and the SMisc register (bit
5).
Slumber mode is cleared by setting the ComWake bit in the Smisc register. This will send a COMWAKE signal to
the device through the Serial ATA link to initiate a Slumber to On sequence. Slumber mode can also be cleared
through receipt of OOB signals from the device.
Hot Plug Support
The state diagram below illustrates the logic to support Hot Plugging.
CR
PhyRdy
Periodically send ComReset
until ComInit received
Normal operation
go_to_CR
dp_phyrdy=0
dp_phyrdy=1
Figure 10. Hot Plug Logic State Diagram
The go_to_CR signal is generated by a timer if the internal logic fails to detect valid signals from the Serial ATA
wire for 200 ns. Logic behavior is as follows:
1.
Initial power-up – A ComReset is generated during initial power up. If a device is present and operational,
the PhyRdy state will be entered. If a device is not present or not responding, the CR state will be entered
and ComReset will be generated every 100 ms.
2.
Device is unplugged – The internal logic detects that no more signal is present on the Serial ATA wire.
The timer will expire after 200 ns and go_to_CR will be asserted; the CR state will be entered and
ComReset will be generated every 100 ms. The internal PHYRDY signal will go false causing an interrupt
to the host driver (PHYRDY change interrupt, bit 16 of SError register; enabled by bit 16 of SIEN register).
3.
Device is plugged in – The device will respond to the ComReset with a ComInit. Normal operation will
commence and the internal logic will detect a PHYRDY signal going true causing an interrupt to the host
driver (PHYRDY change interrupt, bit 16 of SError register; enabled by bit 16 of SIEN register).