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參數(shù)資料
| 型號(hào)： | SII3114CT176 |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP176 |
| 封裝： | TQFP-176 |
| 文件頁(yè)數(shù)： | 124/127頁(yè) |
| 文件大?。?/td> | 564K |
| 代理商： | SII3114CT176 |
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SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
SiI-DS-0103-D
88
2007 Silicon Image, Inc.
Upon reception of an interlocked FIS (FISxxcfg[1:0] = '10'), the Link/Transport Logic sets the
IntrlckFIS bit in the Smisc register. The following describes the possible sequence of events:
Sequence 1:
The Link Logic will continue to receive data while its buffer is being filled up.
IntrlckFIS will cause an interrupt to the host.
The first 7 Dwords of the FIS are available to the host in the RxFIS0 to RxFIS6
registers.The driver will check the FIS type, clean up the PCI section, arm the
DMA controller, and then assert the Rx_IFIS bit in the Smisc register.
The Link/Transport Logic transfers the received FIS, including the header, through
the PCI interface to the host.
When all the data is received with no errors, the Link/Transport Logic will assert the
IFIS_OK bit in the Smisc register. Otherwise one of the error bits will be set in
the Serror register.
The host will set the Accept_IFIS bit to accept or Reject_IFIS to reject the FIS.
If no error is detected inside the frame and the Accept_IFIS bit is asserted, the
Link/Transport Logic will send R_OK to the downstream device. If Reject_IFIS
is asserted or any error is detected, the Link/Transport Logic will respond with
R_ERR. Note that there is an interlock - if the frame is good, it will always wait
for the Accept_IFIS or Reject_IFIS (if not asserted already) before responding.
Sequence 2:
Link/Transport Logic will continue to receive data while its buffer is being filled up.
IntrlckFIS will cause an interrupt to the host.
Host reads the header; the driver will check the FIS type in RxFIS register and
knows that the entire FIS is not larger than the size of RxFIS0 to 6 register.
Host waits for IFIS_OK (if any error detected – the error signals).
If IFIS_OK is received, host reads all data directly via PCI registers and then issues
an Accept_IFIS (Link/Transport Logic to send R_OK) or a Reject_IFIS
(Link/Transport Logic to send R_ERR).
If any error is detected, host can ignore, the Link will respond with R_ERR anyway.
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PDF描述 |
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| SII3124ACBHU | PCI BUS CONTROLLER, PBGA364 |
| SII3512ECTU128 | PCI BUS CONTROLLER, PQFP128 |
| SII3531ACNU | PCI BUS CONTROLLER, QCC48 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SII3114CTU | 制造商:Silicon Image Inc 功能描述:PCI to Serial ATA Controller 176-Pin TQFP 制造商:SILICON 功能描述: |
| SII3124A | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller |
| SII3124ACBHU | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller |
| SII3132 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI Express to 2-Port Serial ATA II Host Controller |
| SII3132CNU | 制造商:Silicon Image Inc 功能描述:PCI Express to Serial ATA Controller 88-Pin QFN |
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