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參數(shù)資料
| 型號： | SCFLXRAYADPTS12 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 53/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | ADAPTER BOARD FRDC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
| 附件類型： | * |
| 適用于相關(guān)產(chǎn)品： | * |
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SCF5250 Data Sheet: Technical Data, Rev. 1.3
6
Freescale Semiconductor
1.2.16
IDE and SmartMedia Interfaces
The SCF5250 system bus allows connection of an IDE hard disk drive or SmartMedia flash card with a
minimum of external hardware. The external hardware consists of bus buffers for address and data and are
intended to reduce the load on the bus and prevent SDRAM and Flash accesses to propagate to the IDE
bus. The control signals for the buffers are generated in the SCF5250.
Low cost version SCF5250LPV100 and SCF5250LAG100 does not run production test for the
IDE/CF/SD/MMC interfaces. Freescale does not guarantee these interfaces will work on these two
devices.
1.2.17
Analog/Digital Converter (ADC)
The six channel ADC is a based on the Sigma-Delta concept with 12-bit resolution. Both the analogue
comparator and digital sections of the ADC are provided internally. An external integrator circuit
(resistor/capacitor) is required, which is driven by the ADC output. A software interrupt is provided when
the ADC measurement cycle is complete.
1.2.18
I2C Module
The two-wire I2C bus interface, which is compliant with the Philips I2C bus standard, is a bidirectional
serial bus that exchanges data between devices. The I2C bus minimizes the interconnection between
devices in the end system and is best suited for applications that need occasional bursts of rapid
communication over short distances among several devices. Bus capacitance and the number of unique
addresses limit the maximum communication length and the number of devices that can be connected.
1.2.19
Chip-Selects
Up to four programmable chip-select outputs provide signals that enable glueless connection to external
memory and peripheral circuits. The base address, access permissions and automatic wait-state insertion
are programmable with configuration registers. These signals also interface to 16-bit ports.
CS0 is active after reset to provide boot-up from external FLASH/ROM.
1.2.20
GPIO Interface
A total of 60 General Purpose inputs and 57 General Purpose outputs are available. These are multiplexed
with various other signals. Seven of the GPIO inputs have edge sensitive interrupt capability.
1.2.21
Interrupt Controller
The interrupt controller provides user-programmable control of a total of 57 interrupts. There are 49
internal interrupt sources. In addition, there are 7 GPIOs where interrupts can be generated on the rising
or falling edge of the pin. All interrupts are autovectored and interrupt levels are programmable.
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