SCF5250 Data Sheet: Technical Data, Rev. 1.3 30 Freescale" />
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型號(hào): SCFLXRAYADPTS12
廠商: Freescale Semiconductor
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SCF5250 Data Sheet: Technical Data, Rev. 1.3
30
Freescale Semiconductor
Figure 7 and Table 25 provide the timing diagram and timing parameters for the UART module.
Figure 7. UART Module AC Timing Definition Diagram
Table 25. UART Module AC Timing Specifications
Num
Characteristic
Min
Max
Units
U1
RXD Valid to BCLK (input setup)
6
ns
U2
BCLK to RXD Invalid (input hold)
0
ns
U3
CTS Valid to BCLK (input setup)
6
ns
U4
BCLK to CTS Invalid (input hold)
0
ns
U5
BCLK to TXD Valid (output valid)
tbd
ns
U6
BCLK to TXD Invalid (output hold)
3
ns
U7
BCLK to RTS Valid (output valid)
tbd
ns
U8
BCLK to RTS Invalid (output hold)
3
ns
BCLK
RXD
CTS
TXD
RTS
U1
U2
U3
U4
U5
U6
U7
U8
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