SCF5250 Data Sheet: Technical Data, Rev. 1.3 32 Freescale" />
參數(shù)資料
型號(hào)： SCFLXRAYADPTS12
廠商： Freescale Semiconductor
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SCF5250 Data Sheet: Technical Data, Rev. 1.3
32
Freescale Semiconductor
Figure 9 provides the I2C-bus and system clock timing diagram and Table 28 provides the I2C-bus output
timing parameters.
Figure 9. I2C and System Clock Timing Relationship
Table 28. I2C Output Bus Timings
Num
Characteristic
96 MHz
Units
Min
Max
M101
1 SCL and SDA are internally synchronized. This setup time must be met only if recognition on a particular clock is required.
SCL, SDA Valid to BCLK (input setup)
2
–
ns
M11
BCLK to SCL, SDA Invalid (input hold)
4.5
–
ns
M122
2 Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, this specification applies only when SCL
or SDA are driven low by the processor. The time required for SCL or SDA to reach a high level depends on external signal capacitance and
pull-up resistor values.
BCLK to SCL, SDA Low (output valid)
–
10
ns
M133
3 Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, this specification applies only when SCL
or SDA are actively being driven or held low by the processor.
BCLK to SCL, SDA Invalid (output hold)
3
–
ns
BCLK
SCL, SDA IN
SCL, SDA OUT
M10
M11
M12
M13
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