參數(shù)資料
型號(hào): SC28L92
廠商: NXP Semiconductors N.V.
英文描述: 3.3V- 5.0V Dual universal asynchronous receiver/transmitter (DUART)(3.3V- 5.0V雙通用異步接收器/傳送器)
中文描述: 3.3 - 5.0V雙路通用異步接收/發(fā)送器(杜阿爾特)(3.3 - 5.0V雙通用異步接收器/傳送器)
文件頁(yè)數(shù): 8/44頁(yè)
文件大?。?/td> 284K
代理商: SC28L92
Philips Semiconductors
Product specification
SC28L92
3.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
2000 Jan 21
8
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D0–D7
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I/O
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PIN
Data Bus
: Bi-directional 3-State data bus used to transfer commands, data and status between the DUART and the
Chip Enable
: Active-Low input signal. When Low, data transfers between the CPU and the DUART are enabled on
D0–D7 as controlled by the WRN, RDN and A0–A3 inputs. When High, places the D0–D7 lines in the 3-State
condition.
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transfer occurs on the rising edge of the signal.
RDN
I
Read Strobe
: When Low and CEN is also Low, causes the contents of the addressed register to be presented on the
data bus. The read cycle begins on the falling edge of RDN.
stops the counter/timer, and puts Channels A and B in the inactive state, with the TxDA and TxDB outputs in the mark
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interrupting conditions are true. This pin requires a pullup device.
X1/CLK
I
Crystal 1
: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When a
to ground (see Figure 11). If X1/CLK is driven from an external source, this pin
must
be left open.
RxDA
I
Channel A Receiver Serial Data Input
: The least significant bit is received first. “Mark” is High; “space” is Low.
RxDB
I
Channel B Receiver Serial Data Input
: The least significant bit is received first. “Mark” is High; “space” is Low.
Channel A Transmitter Serial Data Output
: The least significant bit is transmitted first. This output is held in the “mark”
condition when the transmitter is disabled, idle or when operating in local loop back mode. “Mark” is High; “space” is Low.
TxDB
O
Channel B Transmitter Serial Data Output
: The least significant bit is transmitted first. This output is held in the ‘mark’
Output 0
: General purpose output or Channel A request to send (RTSAN, active-Low). Can be deactivated
automatically on receive or transmit.
OP1
O
Output 1
: General-purpose output or Channel B request to send (RTSBN, active-Low). Can be deactivated
output, or Channel B receiver 1X clock output.
OP4
O
Output 4
: General purpose output or Channel A open-drain, active-Low, RxA interrupt ISR[1] output.
IP1
I
Input 1
: General purpose input or Channel B clear to send active-Low input (CTSBN).
IP2
I
Input 2
: General-purpose input or counter/timer external clock input.
IP3
I
Input 3
: General purpose input or Channel A transmitter external clock input (TxCA). When the external clock is used
by the transmitter, the transmitted data is clocked on the falling edge of the clock.
the receiver, the received data is sampled on the rising edge of the clock.
Input 5
: General purpose input or Channel B transmitter external clock input (TxCB). When the external clock is used
by the transmitter, the transmitted data is clocked on the falling edge of the clock.
the receiver, the received data is sampled on the rising edge of the clock.
CC
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Write Strobe
: When Low and CEN is also Low, the contents of the data bus is loaded into the addressed register. The
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INTRN
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Interrupt Request
: Active-Low, open-drain, output which signals the CPU that one or more of the eight maskable
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