參數(shù)資料
型號(hào)： SC28L92
廠商： NXP Semiconductors N.V.
英文描述： 3.3V- 5.0V Dual universal asynchronous receiver/transmitter (DUART）(3.3V- 5.0V雙通用異步接收器/傳送器)
中文描述： 3.3 - 5.0V雙路通用異步接收/發(fā)送器（杜阿爾特）（3.3 - 5.0V雙通用異步接收器/傳送器）
文件頁數(shù)： 33/44頁
文件大?。?/td> 284K
代理商： SC28L92
Philips Semiconductors
Product specification
SC28L92
3.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
2000 Jan 21
33
ISR—Interrupt Status Register
This register provides the status of all potential interrupt sources. The contents of this register are masked by the Interrupt Mask Register (IMR).
If a bit in the ISR is a ‘1’ and the corresponding bit in the IMR is also a ‘1’, the INTRN output will be asserted (Low). If the corresponding bit in
the IMR is a zero, the state of the bit in the ISR has no effect on the INTRN output. Note that the IMR does not mask the reading of the ISR - the
true status will be provided regardless of the contents of the IMR. The contents of this register are initialized to H‘00’ when the DUART is reset.
ISR INTERRUPT STATUS REGISTER
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Addr
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Bit 7
áá
áá
0x05
BIT 6
á
BIT 5
BIT 4
áá
áá
0 = not active
BIT 3
BIT 2
á
BIT 1
áá
áá
0 = not active
BIT 0
ISR
0 = not active
á
á
CHANGE
ááá
ááá
INPUT
á
ááá
ááá
0 = not active
DELTA
á
á
á
0 = not active
1 = active
á
ááá
ááá
TxRDY B
á
á
ááá
ááá
0 = not active
Counter
á
0 = not active
1 = active
Delta
á
á
ááá
ááá
RxRDY/
á
á
ááá
ááá
0 = not active
á
á
TxRDY A
1 = active
1 = active
1 = active
1 = active
1 = active
1 = active
ISR[7]—Input Port Change Status
This bit is a ‘1’ when a change-of-state has occurred at the IP0, IP1,
IP2, or IP3 inputs and that event has been selected to cause an
interrupt by the programming of ACR[3:0]. The bit is cleared when
the CPU reads the IPCR.
ISR[6]—Channel B Change In Break
This bit, when set, indicates that the Channel B receiver has
detected the beginning or the end of a received break. It is reset
when the CPU issues a Channel B ‘reset break change interrupt’
command.
ISR[5]—RxB Interrupt
This bit indicates that the channel B receiver is interrupting
according to the fill level programmed by the MR0 and MR1
registers. This bit has a different meaning than the receiver
ready/full bit in the status register.
ISR[4]—TxB Interrupt
This bit indicates that the channel B transmitter is interrupting
according to the interrupt level programmed in the MR0[5:4] bits.
This bit has a different meaning than the Tx RDY bit in the status
register.
ISR[3]—Counter Ready.
In the counter mode, this bit is set when the counter reaches
terminal count and is reset when the counter is stopped by a stop
counter command.
In the timer mode, this bit is set once each cycle of the generated
square wave (every other time that the counter/timer reaches zero
count). The bit is reset by a stop counter command. The command,
however, does not stop the counter/timer.
ISR[2]—Channel A Change in Break
This bit, when set, indicates that the Channel A receiver has
detected the beginning or the end of a received break. It is reset
when the CPU issues a Channel A ‘reset break change interrupt’
command.
ISR[1]—RxA Interrupt
This bit indicates that the channel A receiver is interrupting
according to the fill level programmed by the MR0 and MR1
registers. This bit has a different meaning than the receiver
ready/full bit in the status register.
ISR[0]—TxA Interrupt
This bit indicates that the channel A transmitter is interrupting
according to the interrupt level programmed in the MR0[5:4] bits.
This bit has a different meaning than the Tx RDY bit in the status
register.
IMR—Interrupt Mask Register
The programming of this register selects which bits in the ISR causes an interrupt output. If a bit in the ISR is a ‘1’ and the corresponding bit in
the IMR is also a ‘1’ the INTRN output will be asserted. If the corresponding bit in the IMR is a zero, the state of the bit in the ISR has no effect
on the INTRN output. Note that the IMR does not mask the programmable interrupt outputs OP3–OP7 or the reading of the ISR.
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Addr
Bit 7
BIT 6
BIT 5
BIT 4
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BIT 3
BIT 2
BIT 1
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BIT 0
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áá
áá
á
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PORT
CHANGE
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Break B
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áá
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á
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á
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Ready
á
áá
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Break A
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FFULL A
á
ááá
ááá
A
á
á
0x05
á
0 = not
á
0 = not
á
0 = not
á
0 = not
á
0 = not
á
0 = not
á
0 = not
á
0 = not
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