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參數(shù)資料

型號：	SC28L92
廠商：	NXP Semiconductors N.V.
英文描述：	3.3V- 5.0V Dual universal asynchronous receiver/transmitter (DUART）(3.3V- 5.0V雙通用異步接收器/傳送器)
中文描述：	3.3 - 5.0V雙路通用異步接收/發(fā)送器（杜阿爾特）（3.3 - 5.0V雙通用異步接收器/傳送器）
文件頁數(shù)：	20/44頁
文件大小：	284K
代理商：	SC28L92

Philips Semiconductors

Product specification

SC28L92

3.3V–5.0V Dual Universal Asynchronous

Receiver/Transmitter (DUART)

2000 Jan 21

MR1A[4:3]or MR1B[4:3] to ‘11’ for Channels A and B, respectively.

In this mode of operation, a ‘master’ station transmits an address

character followed by data characters for the addressed ‘slave’

station. The slave stations, with receivers that are normally disabled,

examine the received data stream and ‘wakeup’ the CPU (by setting

RxRDY)only upon receipt of an address character. The CPU

compares the received address to its station address and enables

the receiver if it wishes to receive the subsequent data characters.

Upon receipt of another address character, the CPU may disable the

receiver to initiate the process again.

A transmitted character consists of a start bit, the programmed

number of data bits, and Address/Data (A/D) bit, and the

programmed number of stop bits. The polarity of the transmitted A/D

bit is selected by the CPU by programming bit MR1A[2]/MR1B[2].

MR1A[2]/MR1B[2] = 0 transmits a zero in the A/D bit position, which

identifies the corresponding data bits as data while

MR1A[2]/MR1B[2] = 1 transmits a one in the A/D bit position, which

identifies the corresponding data bits as an address. The CPU

should program the mode register prior to loading the corresponding

data bits into the TxFIFO.

In this mode, the receiver continuously looks at the received data

stream, whether it is enabled or disabled. If disabled, it sets the

RxRDY status bit and loads the character into the RxFIFO if the

received A/D bit is a one (address tag), but discards the received

character if the received A/D bit is a zero (data tag). If enabled, all

received characters are transferred to the CPU via the RxFIFO. In

either case, the data bits are loaded into the data FIFO while the

A/D bit is loaded into the status FIFO position normally used for

parity error (SRA[5] or SRB[5]). Framing error, overrun error, and

break detect operate normally whether or not the receive is enabled.

PROGRAMMING

The operation of the DUART is programmed by writing control words

into the appropriate registers. Operational feedback is provided via

status registers which can be read by the CPU. The addressing of

the registers is described in Table 1.

The contents of certain control registers are initialized to zero on

RESET. Care should be exercised if the contents of a register are

changed during operation, since certain changes may cause

operational problems.

For example, changing the number of bits per character while the

transmitter is active may cause the transmission of an incorrect

character. In general, the contents of the MR, the CSR, and the

OPCR should only be changed while the receiver(s) and

transmitter(s) are not enabled, and certain changes to the ACR

should only be made while the C/T is stopped.

Each channel has 3 mode registers (MR0, 1, 2) which control the

basic configuration of the channel. Access to these registers is

controlled by independent MR address pointers. These pointers are

set to 0 or 1 by MR control commands in the command register

“Miscellaneous Commands”. Each time the MR registers are

accessed the MR pointer increments, stopping at MR2. It remains

pointing to MR2 until set to 0 or 1 via the miscellaneous commands

of the command register. The pointer is set to 1 on reset for

compatibility with previous Philips Semiconductors UART software.

Mode, command, clock select, and status registers are duplicated

for each channel to provide total independent operation and control.

Refer to Table 2 for register bit descriptions. The reserved registers

at addresses H‘02’ and H‘0A’ should never be read during normal

operation since they are reserved for internal diagnostics.

Table 1. SC28L92 register addressing READ (RDN = 0), WRITE (WRN = 0)

Mode Register A (MR0A, MR1A, MR2A)

Status Register A (SRA)

Reserved

Interrupt Status Register (ISR)

Counter/Timer Upper (CTU)

Counter/Timer Lower (CTL)

Mode Register B (MR0B, MR1B, MR2B)

Rx Holding Register B (RxFIFOB)

Interrupt vector (68K mode)

Misc. register (Intel mode), IVR Motorola mode

Input Port (IPR)

Start Counter Command

1. The three MR registers are accessed via the MR Pointer and Commands 0x1n and 0xBn (where n = represents receiver and transmitter enable bits)

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Mode Register A (MR0A, MR1A, MR2A)

Clock Select Register A (CSRA)

Command Register A (CRA)

C/T Upper Preset Register (CTPU)

C/T Lower Preset Register (CTPL)

Mode Register B (MR0B, MR1B, MR2B)

Misc. register (Intel mode), IVR Motorola mode

Output Port Conf. Register (OPCR)

Set Output Port Bits Command (SOPR)

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