參數(shù)資料
型號: SC28L92
廠商: NXP Semiconductors N.V.
英文描述: 3.3V- 5.0V Dual universal asynchronous receiver/transmitter (DUART)(3.3V- 5.0V雙通用異步接收器/傳送器)
中文描述: 3.3 - 5.0V雙路通用異步接收/發(fā)送器(杜阿爾特)(3.3 - 5.0V雙通用異步接收器/傳送器)
文件頁數(shù): 32/44頁
文件大?。?/td> 284K
代理商: SC28L92
Philips Semiconductors
Product specification
SC28L92
3.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
2000 Jan 21
32
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ACR—Auxiliary Control Register
Addr
Bit 7
BIT 6
MoCounter Timer Mode
BIT 5
BIT 4
BIT 3
BIT 2
Deenable
BIT 1
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1 = enabled
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BIT 0
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1 = set 2
ACR
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Select
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BRG SET
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1 = enabled
enable
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1 = enabled
Delta IP3 int
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enable
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1 = enabled
enable
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Delta IP3 int
ACR[7]—Baud Rate Generator Set Select
This bit selects one of two sets of baud rates to be generated by the
BRG (see Table 5).
The selected set of rates is available for use by the Channel A and
B receivers and transmitters as described in CSRA and CSRB.
Baud rate generator characteristics are given in Table 6.
ACR[6:4]—Counter/Timer Mode And Clock Source Select
This field selects the operating mode of the counter/timer and its
clock source as shown in Table 7
ACR [3:0]—IP3, IP2, IP1, IP0 Change-of-State Interrupt Enable
This field selects which bits of the input port change register (IPCR)
cause the input change bit in the interrupt status register (ISR [7]) to
be set. If a bit is in the ‘on’ state the setting of the corresponding bit
in the IPCR will also result in the setting of ISR [7], which results in
the generation of an interrupt output if IMR [7] = 1. If a bit is in the
‘off’ state, the setting of that bit in the IPCR has no effect on ISR [7].
NOTE:
The timer mode generates a square wave
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000
001
Counter
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Counter
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Counter
External (IP2) divided by 16
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External (IP2)
TxCA - 1X clock of Channel A transmitter
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Counter
TxCB - 1X clock of Channel B transmitter
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Crystal or external clock (X1/CLK)
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111
Timer
Crystal or external clock (X1/CLK) divided
by 16
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Crystal or external clock (X1/CLK) divided
IPCR INPUT PORT CHANGE REGISTER
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IPCR [7:4]—IP3, IP2, IP1, IP0 Change-of-State
These bits are set when a change-of-state, as defined in the input
port section of this data sheet, occurs at the respective input pins.
They are cleared when the IPCR is read by the CPU. A read of the
IPCR also clears ISR [7], the input change bit in the interrupt status
register. The setting of these bits can be programmed to generate
an interrupt to the CPU.
Addr
Bit 7
BIT 6
BIT 5
Delta IP3
BIT 4
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IPCR [3:0]—IP3, IP2, IP1, IP0 Change-of-State
These bits provide the current state of the respective inputs. The
information is unlatched and reflects the state of the input pins at the
time the IPCR is read.
BIT 3
BIT 2
1 = High
BIT 1
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BIT 0
IPCR
Delta IP3
Delta IP3
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change
1 = change
Delta IP3
IP 3
IP 2
IP 1
IP 0
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1 = change
0x04
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change
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1 = change
0 = no
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change
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0 = no
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1 = change
0 = no
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change
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1 = High
0 = no
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0 = low
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0 = low
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1 = High
0 = low
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0 = low
1 = High
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