參數(shù)資料
型號: SC28L92
廠商: NXP Semiconductors N.V.
英文描述: 3.3V- 5.0V Dual universal asynchronous receiver/transmitter (DUART)(3.3V- 5.0V雙通用異步接收器/傳送器)
中文描述: 3.3 - 5.0V雙路通用異步接收/發(fā)送器(杜阿爾特)(3.3 - 5.0V雙通用異步接收器/傳送器)
文件頁數(shù): 35/44頁
文件大小: 284K
代理商: SC28L92
Philips Semiconductors
Product specification
SC28L92
3.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
2000 Jan 21
35
thus, called RTSAN for RxA and RTSBN for RxB. RTSAN is on pin
OP0 and RTSBN is on OP1. A receiver’s RTS output will usually be
connected to the CTS input of the associated transmitter. Therefore,
one could say that RTS and CTS are different ends of the same
wire!
MR2(4) is the bit that allows the transmitter to be controlled by the
CTS pin (IP0 or IP1). When this bit is set to one AND the CTS input
is driven high, the transmitter will stop sending data at the end of the
present character being serialized. It is usually the RTS output of
the receiver that will be connected to the transmitter’s CTS input.
The receiver will set RTS high when the receiver FIFO is full AND
the start bit of the ninth or 17th character is sensed. Transmission
then stops with nine or 17 valid characters in the receiver. When
MR2(4) is set to one, CTSN must be at zero for the transmitter to
operate. If MR2(4) is set to zero, the IP pin will have no effect on
the operation of the transmitter. MR1(7) is the bit that allows the
receiver to control OP0. When OP0 (or OP1) is controlled by the
receiver, the meaning of that pin will be.
RESETN
t
RES
SD00696
RESETN
t
RES
80XXX Mode
68XXX Mode
Figure 4. Reset Timing
A0–A3
CEN
t
AS
t
CS
t
CH
RDN
t
RW
t
RWD
D0–D7
(READ)
t
DD
t
DF
FLOAT
FLOAT
VALID
NOT
VALID
WDN
t
RWD
VALID
D0–D7
(WRITE)
t
DS
t
DH
t
AH
SD00087
Figure 5. Bus Timing (80XXX mode)
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