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| 型號(hào)： | SC28L92 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 3.3V- 5.0V Dual universal asynchronous receiver/transmitter (DUART）(3.3V- 5.0V雙通用異步接收器/傳送器) |
| 中文描述： | 3.3 - 5.0V雙路通用異步接收/發(fā)送器（杜阿爾特）（3.3 - 5.0V雙通用異步接收器/傳送器） |
| 文件頁(yè)數(shù)： | 22/44頁(yè) |
| 文件大?。?/td> | 284K |
| 代理商： | SC28L92 |
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Philips Semiconductors
Product specification
SC28L92
3.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
2000 Jan 21
22
CTPL
–
COUNTER TIMER PRESET REGISTER, LOWER
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ACR
–
AUXILIARY CONTROL REGISTER AND CHANGE OF STATE CONTROL
Bit 7
Bit 6:4
Bit 3
Baud Group
Counter Timer mode and clock select
Enable IP3
Bits 7:0
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8 LSB of the BRG Timer divisor.
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IPCR
–
INPUT PORT CHANGE REGISTER
Delta IP3
Delta IP2
Bit 2
Bit 1
Bit 0
Enable IP2
Enable IP1
Enable IP0
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State of IP
Delta IP1
Delta IP0
State of IP3
State of IP2
State of IP1
State of IP0
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Bit 7
BIT 6
Set OP 7
Set OP 6
State of IP 3
State of IP 2
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State of IP 6
State of IP 5
State of IP 4
State of IP1
State of IP 0
BIT 5
Set OP 5
BIT 4
Set OP 4
BIT 3
Set OP 3
BIT 2
BIT 1
BIT 0
Set OP 2
Set OP 1
Set OP 0
ROPR – RESET OUTPUT PORT BITS (OPR)
Bit 7
BIT 6
Reset OP 7
Reset OP 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reset OP 5
Reset OP 4
Reset OP 3
Reset OP 2
Reset OP 1
Reset OP 0
OPCR OUTPUT PORT CONFIGURATION REGISTER (NOTE OP1 AND OP0 ARE THE RTSN OUTPUT AND
ARE CONTROLLED BY THE MR REGISTER)
Bit 7
BIT 6
BIT 5
Configure OP7
Configure OP6
Configure OP5
Configure OP4
BIT 4
BIT(3:2)
BIT(1:0)
Configure OP3
Configure OP2
REGISTER DESCRIPTIONS Mode Registers
MR0A
Mode Register 0. MR0 is accessed by setting the MR pointer to 0 via the command register command B.
Addr
Bit 7
BIT 6
BITS 5:4
MR0B
WATCHDOG
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MR0[7]
—This bit controls the receiver watch dog timer. 0 = disable,
1 = enable. When enabled, the watch dog timer will generate a
receiver interrupt if the receiver FIFO has not been accessed within
64 bit times of the receiver 1X clock. This is used to alert the control
processor that data is in the RxFIFO that has not been read. This
situation may occur when the byte count of the last part of a
message is not large enough to generate an interrupt.
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See Table 4
BIT 3
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BIT 2
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3 or more bytes in FIFO
BIT 1
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Set to 0
BIT 0
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Rx
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description
RxINT BIT 2
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EXTENDED II
BAUD RATE
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EXTENDED 1
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0x00
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0 = 8 byte FIFO
1 = 16 byte FIFO
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0 = Normal
1 = Extend II
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0 = Normal
MR0[6]
—Bit 2 of receiver FIFO interrupt level. This bit along with Bit
6 of MR1 sets the fill level of the FIFO that generates the receiver
interrupt.
MR0[6] MR1[6]
Note that this control is split between MR0 and
MR1. This is for backward compatibility to the SC2692 and
SCN2681.
Table 3. Receiver FIFO interrupt fill level
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01
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11
10
8 bytes in FIFO (Rx FULL)
6 or more bytes in FIFO
Table 3a. Receiver FIFO interrupt fill
level(MR0(3)=1 (16 bytes)
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01
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MR0[6] MR1[6]
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00
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10
8 or more bytes in FIFO
Interrupt Condition
1 or more bytes in FIFO (Rx RDY)
12 or more bytes in FIFO
11
16 bytes in FIFO (Rx FULL)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC28L92A1A | 制造商:NXP Semiconductors 功能描述:UART DUAL 3.3V OR 5V SMD 28L92 |
| SC28L92A1A,512 | 功能描述:UART 接口集成電路 3V-5V 2CH UART INTEL/MOT INTRF RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC28L92A1A,518 | 功能描述:UART 接口集成電路 3V-5V 2CH UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC28L92A1A,529 | 功能描述:UART 接口集成電路 3V-5V 2CH UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC28L92A1A512 | 制造商:NXP Semiconductors 功能描述:IC DUAL UART FIFO 1MBPS 5.5V LCC-44 |
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