參數(shù)資料
    型號: SAF-C513A-HN
    廠商: INFINEON TECHNOLOGIES AG
    元件分類: 微控制器/微處理器
    英文描述: 8-BIT, EEPROM, 8 MHz, MICROCONTROLLER, PQCC44
    封裝: PLASTIC, LCC-44
    文件頁數(shù): 88/128頁
    文件大?。?/td> 1837K
    代理商: SAF-C513A-HN
    On-Chip Peripheral Units
    Semiconductor Group
    6-29
    6.3.2 Serial Port Control Register
    The serial port control and status register is the special function register SCON. This register
    contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and
    RB8) and the serial port interrupt bits (TI and RI).
    Special Function Register SCON (Address 98H)
    Reset Value : 00H
    Bit
    Function
    SM0
    SM1
    0
    1
    0
    1
    Serial Mode Select Bits
    Serial mode 0:
    Shift register, fixed baud rate (
    f
    OSC/12)
    Serial mode 1:
    8-bit UART, variable baud rate
    Serial mode 2:
    9-bit UART, fixed baud rate (
    f
    OSC/64 or fOSC/32)
    Serial mode 3:
    9-bit UART, variable baud rate
    SM2
    Multiprocessor Communication Select
    Enables the multiprocessor communication feature in modes 2 and 3. In mode 2
    or 3, if SM2 is set to 1 then RI will not be activated if the received 9th data bit (RB8)
    is 0. In mode 1, if SM2 = 1 then RI will not be activated if a valid stop bit was not
    received. In mode 0, SM2 should be 0.
    REN
    Receiver Enable
    Enables serial reception. Set by software to enable reception. Clear by software
    to disable reception.
    TB8
    Transmit Bit 8
    Is the 9th data bit that will be transmitted in modes 2 and 3. Set or clear by
    software as desired.
    RB8
    Receive Bit 8
    In modes 2 and 3, is the 9th data bit that was received. In mode 1, if SM2 = 0, RB8
    is the stop bit that was received. In mode 0, RB8 is not used.
    TI
    Transmit Interrupt Flag
    Is transmit interupt flag. Set by hardware at the end of the 8th bit time in mode 0,
    or at the beginning of the stop bit in the other modes, in any serial transmission.
    Must be cleared by software.
    RI
    Receive Interrupt Flag
    Is receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0,
    or halfway through the stop bit time in the other modes, in any serial reception
    (except see SM2). Must be cleared by software.
    SM0
    SM1
    SM2
    REN
    98H
    SCON
    Bit No.
    7
    65
    43
    21
    0
    MSB
    LSB
    TB8
    RB8
    TI
    RI
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