參數(shù)資料
型號(hào): SAF-C513A-HN
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 8-BIT, EEPROM, 8 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁(yè)數(shù): 104/128頁(yè)
文件大?。?/td> 1837K
代理商: SAF-C513A-HN
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)當(dāng)前第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)
Semiconductor Group
6-44
On-Chip Peripheral Units
As the SSC is a synchronous serial interface, for each transfer a dedicated clock signal sequence
must be provided. The SSC has implemented a clock control circuit, which can generate the clock
via a baud rate generator in the master mode, or receive the transfer clock in the slave mode. The
clock signal is fully programmable for clock polarity and phase. The pin used for the clock signal is
P1.2 / SCLK.
When operating in slave mode, a slave select input SLS is provided which enables the SSC
interface and also will control the transmitter output. The pin used for this is P1.5 / SLS. In addition
to this there is an additional option for controlling the transmitter output by software.
The SSC control block is responsible for controlling the different modes and operation of the SSC,
checking the status, and generating the respective status and interrupt signals.
6.4.2 General Operation of the SSC
After initialization of the SSC, the data to be transmitted has to be written into the shift register
STB.
In master mode this will initiate the transfer by resetting the baudrate generator and starting the
clock generation. The control bits CPOL and CPHA in the SSCCON register determine the idle
polarity of the clock (polarity between transfers) and which clock edges are used for shifting and
sampling data (see figure 6-6-32).
While the transmit data in the shift register is shifted out bit per bit starting with the MSB, the
incoming receive data are shifted in, synchronized with the clock signal at pin SCLK. When the eight
bits are shifted out (and the same number is of course shifted in), the contents of the shift register
is transferred to the receive buffer register SRB, and the transmission complete flag TC is set. If
enabled an interrupt request will be generated.
After the last bit has been shifted out and was stable for one bit time, the STO output will be switched
to "1" (forced "1"), the idle state of STO. This allows connection of standard asynchronous receivers
to the SSC in master mode.
In slave mode the device will wait for the slave select input SLS to be activated (=low) and then will
shift in the data provided on the receive input according to the clock provided at the SCLK input and
the setting of the CPOL ad CPHA bits. After eight bits have been shifted in, the content of the shift
register is transferred to the receive buffer register and the transmission complete flag TC is set. If
the transmitter is enabled in slave mode (TEN bit set to 1), the SSC will shift out at STO at the same
time the data currently contained in the shift register. If the transmitter is disabled, the STO output
will remain in the tristate state. This allows more than one slave to share a common select line.
If SLS is inactive the SSC will be inactive and the content of the shift register will not be modified.
6.4.3 Enable/Disable Control
Bit SSCEN of the SSCCON register globally enables or disables the synchronous serial interface.
Setting SSCEN to “0” stops the baud rate generator and all internal activities of the SSC. Current
transfers are aborted. The alternate output functions at pins P1.3/SRI, P1.4/STO, P1.5/SLS, and
P1.2/SCLK return to their primary I/O port function. These pins can now be used for general
purpose I/O.
相關(guān)PDF資料
PDF描述
SAF-C515A-LM 8-BIT, 18 MHz, MICROCONTROLLER, PQFP80
SAF-C515C-8EMCA 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP80
SAF-C517A-4R24M 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP100
SAF-C868-1RR 8-BIT, MROM, 40 MHz, MICROCONTROLLER, PDSO38
SAF-C868-1SR 8-BIT, 40 MHz, MICROCONTROLLER, PDSO38
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAF-C513AO 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-bit CMOS Microcontroller
SAF-C515 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit CMOS Microcontroller
SAF-C515-1R24M 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit CMOS Microcontroller
SAF-C515-1RM 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit CMOS Microcontroller
SAF-C515A-4R 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8-Bit CMOS Microcontroller