參數(shù)資料
型號(hào): SAF-C513A-HN
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 8-BIT, EEPROM, 8 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁(yè)數(shù): 60/128頁(yè)
文件大?。?/td> 1837K
代理商: SAF-C513A-HN
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Semiconductor Group
6-4
On-Chip Peripheral Units
The described activating and deactivating of the four different transistors results in four states which
can be :
– input low state (IL), p2 active only
– input high state (IH) = steady output high state (SOH), p2 and p3 active
– forced output high state (FOH), p1, p2 and p3 active
– output low state (OL), n1 active
If a pin is used as input and a low level is applied, it will be in IL state, if a high level is applied, it
will switch to IH state.
If the latch is loaded with "0", the pin will be in OL state.
If the latch holds a "0" and is loaded with "1", the pin will enter FOH state for two cycles and then
switch to SOH state. If the latch holds a "1" and is reloaded with a "1" no state change will occur.
At the beginning of power-on reset the pins will be in IL state (latch is set to "1", voltage level on
pin is below of the trip point of p3). Depending on the voltage level and load applied to the pin, it will
remain in this state or will switch to IH (=SOH) state.
If it is is used as output, the weak pull-up p2 will pull the voltage level at the pin above p3’s trip point
after some time and p3 will turn on and provide a strong "1". Note, however, that if the load exceeds
the drive capability of p2 (
I
IL), the pin might remain in the IL state and provide a week "1" until the
first 0-to-1 transition on the latch occurs. Until this the output level might stay below the trip point of
the external circuitry.
The same is true if a pin is used as bidirectional line and the external circuitry is switched from
output to input when the pin is held at "0" and the load then exceeds the p2 drive capabilities.
If the load exceeds
I
IL
the pin can be forced to “1“ by writing a “0“ followed by a “1“ to the port pin..
The driver and control structure of the port pins used for the alternate functions of the SSC have
been modified to provide the following features:
– P1.2 when used as SSC clock output will become a true push-pull output
– P1.3 when used as SSC receiver input will become an input without pullups.
– P1.4 when used as SSC transmitter output will become a true push-pull output with tristate
capability
– P1.5 when used as SSC slave select input will directly control the tristate condition of P1.4.
The modified port structure is illustrated in figures 6-b and 6-c.
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