參數(shù)資料
型號: SAF-C513A-HN
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 8-BIT, EEPROM, 8 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 127/128頁
文件大小: 1837K
代理商: SAF-C513A-HN
Power Saving Mode
Semiconductor Group
8-2
8.1
Idle Mode
In the idle mode the oscillator of the C511/513 continues to run, but the CPU is gated off from the
clock signal. However, the interrupt system, the serial port, and all timers are further provided with
the clock. The CPU status is preserved in its entirety: the stack pointer, program counter, program
status word, accumulator, and all other registers maintain their data during idle mode.
The reduction of power consumption, which can be achieved by this feature depends on the number
of peripherals running.
If all timers are stopped and the serial interface is not running, the maximum power reduction can
be achieved. This state is also the test condition for the idle mode
I
CC.
So the user has to take care which peripheral should continue to run and which has to be stopped
during idle mode. Also the state of all port pins – either the pins controlled by their latches or
controlled by their secondary functions – depends on the status of the controller when entering idle
mode.
Normally the port pins hold the logical state they had at the time idle mode was activated. If some
pins are programmed to serve their alternate functions they still continue to drive the output during
idle mode if the assigned function is on. This applies also to the serial interface in case it cannot
finish reception or transmission during normal operation. The control signals ALE and PSEN are
held at logic high levels.
Table 8-1
Status of External Pins During Idle and Power-Down Mode
Outputs
Last Instruction Executed from
Internal Code Memory
Last Instruction Executed from
External Code Memory
Idle
Power-Down
Idle
Power-Down
ALE
High
Low
High
Low
PSEN
High
Low
High
Low
Port 0
Data
Address
Float
Port 1
Data/alternate
outputs
Data/alternate
outputs
Data/alternate
outputs
Data/alternate
outputs
Port 2
Data
Address
Data
Port 3
Data/alternate
outputs
Data/last output
Data/alternate
outputs
Data/last output
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