參數(shù)資料
型號(hào): SAB82525N
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 4M bps, MULTI PROTOCOL CONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 79/126頁
文件大?。?/td> 730K
代理商: SAB82525N
Semiconductor Group
56
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Summary
The features of the different clock modes are summarized in table 6.
Table 6
Clock Modes of HSCX
Note: 1) The maximum data rate in an externally clocked operating mode is 4.1 Mbit/s. In an
internally clocked operating mode with an external reference clock, or using the OSC,
the maximum clock rate is 12 MHz or 19.2 MHz if the scaling factor of the BRG is
programmed to 1. The maximum data rate will be 1200 kbit/s.
2) The ratio between the receive frequency (fr) and the transmit frequency (fx) for a
channel must satisfy the condition fr/fx less than 3 in clock modes 0, 2, 6; there are no
restrictions on the phase shift. Slower transmit data rates can be realized with receive
and transmit strobes (clock mode 1).
3) The clock modes 4, 6, 7 use the internal OSC and need an external quartz crystal to
be connected at the RxCLK A-AxCLK A pins.
It is not necessary to use two separate crystals for the two serial channels, instead it is
sufficient to apply the crystal to channel A and provide the reference clock for channel
B by externally connecting the AxCLKA and RxCLKB pins. The SAB 82526 also uses
the RxCLK A-AxCLK A pins to connect to an external quartz crystal.
Channel Configuration
Clock Sources
Control Sources
Timer
Source
Clock Mode
CCR1
CM2, CM1, CM0
CCR2
Output
via
TxCLK
TSS
TIO
BRG
DPLL
REC
TRM
CD
R-Strobe
X-Strobe
F-Sync
TCP
0
1
2
3
4
5
6
7
0
1
0
1
0
1
0
1
0
1
0
1
RxCLK
OSC
BRG
BRG
RxCLK
DPLL
OSC
RxCLK
DPLL
TxCLK
RxCLK
TxCLK
BRG/16
DPLL
OSC
RxCLK
TxCLK
BRG/16
DPLL
AxCLK
AxCLK
TxCLK
TxCLK
TxCLK
TxCLK
AxCLK
(TSAR)
TxCLK
(TSAX)
AxCLK
BRG/16
DPLL
OSC
TS-Control
BRG/16
DPLL
TxCLK
RxCLK
TxCLK
DPLL
OSC
RxCLK
TxCLK
BRG/16
DPLL
SAB 82525
SAB 82526
SAF 82525
SAF 82526
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參數(shù)描述
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