參數(shù)資料
型號: SAB82525N
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 4M bps, MULTI PROTOCOL CONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 121/126頁
文件大小: 730K
代理商: SAB82525N
Semiconductor Group
94
SAB 82525
SAB 82526
SAF 82525
SAF 82526
RAH1
(26/66)
70
RAH1
CRI
0
In operating modes that provide high byte address recognition, the high byte of the received
address is compared with the individual programmable values in RAH1, or RAH2.
RAH1 … Value of the first individual high address byte
The setting of the CRI bit affects the meaning of the C/R bit in RSTA as follows:
Receive Address Byte High Register 1 (WRITE)
CRI … Command/Response Interpretation (auto-mode and non-auto mode only)
Commands received
Responses received
C/R meaning
0
C/R value
1
CRI = 1
1
0
CRI = 0
Important: If the 1 byte address field is selected in auto-mode, RAH1 must be set to 00H.
RAH2
(27/67)
70
RAH2
MCS
0
Receive Address Byte High Register 2 (WRITE)
10
RAH2 … Value of second individual programmable high address byte.
MCS … Module Count Select; valid in auto-mode only.
0 … basic operation (modulo 8)
1 … extended operation (modulo 128)
The MCS bit adjusts the control field format according to the HDLC (ISDN/LAPD).
When modulo 128 is selected, in auto-mode the "RHCR" register contains compressed
information of the extended control field (see RHCR, register description). RAH1, RAH2
registers are used in auto and non-auto operating modes when a 2-byte address field
has been selected (MODE.ADM = 1) and in the transparent mode 0.
RAH2 has to be initialized.
Note:
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