參數(shù)資料
型號: SAB82525N
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 4M bps, MULTI PROTOCOL CONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 63/126頁
文件大小: 730K
代理商: SAB82525N
Semiconductor Group
41
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Table 2
Receive Interrupts
RECEIVE INTERRUPTS
RPF
Receive Pool Full
(ISTA)
*Only activated in Interrupt Mode!
Activated as soon as 32-bytes are stored in
the RFIFO but the message is not yet
completed.
RME
Receive Message End
(ISTA)
Interrupt Mode:
Activated if either one message up to 32 bytes
or the last part of a message with more than
32 bytes is stored in the RFIFO, i.e. after the
reception of the CRC and closing flag
sequence.
DMA Mode:
Activated after the complete message has
been read out by the DMA controller.
RFO
Receive Frame Overflow
(EXIR)
Activated if a complete frame could not be
stored due to occupied RFIFO, i.e. the RFIFO
is full and the HSCX has detected the start of
a new frame.
RFS
Receive Frame Start
(EXIR)
*Only activated if enabled by setting the RIE
bit in CCR2 register.
Activated after the start of a valid frame has
been detected, i.e. after a valid address check
in
operation
modes
providing
address
recognition, otherwise after the opening flag
(transparent mode 0), delayed by two bytes.
After an RFS interrupt, the contents of
– RHCR
– RAL1
– RSTA – bit 3-0
are valid and can be read by the CPU.
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