參數(shù)資料
型號: SAB82525N
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 4M bps, MULTI PROTOCOL CONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 36/126頁
文件大?。?/td> 730K
代理商: SAB82525N
Semiconductor Group
17
82525
82526
82525
82526
SAB
SAF
1.2 System Integration
General Aspects
Figure 2 gives a general overview of the system integration of HSCX.
Figure 2
General System Integration of HSCX
The HSCX bus interface consists of an 8-bit bidirectional data bus (D0–D7), seven address
line inputs (A0–A6), three control inputs (RD/DS, WR/R/W, CS), one interrupt request output
(INT) and a 4-channel DMA interface (DRQTA, DRQRA, DACKA, DRQTB, DRQRB, DACKB).
Mode input pins (strapping options) allow the bus interface to be configured for either Siemens/
Intel or Motorola environment.
Generally, there are two types of transfers occurring via the system bus:
– command/status transfers, which are always controlled by the CPU. The CPU sets the
operation mode (initialization), controls function sequences and gets status information by
writing or reading the HSCX’s registers (via CS, WR or RD, and register address via A0-A6).
– data transfers, which are effectively performed by DMA without CPU interaction using the
HSCX’s DMA interface (DMA mode). Optionally, interrupt controlled data transfer can be
done by the CPU (interrupt mode).
Memory
CPU
CS
System Bus
HSCX
DATA
DRQTA,
DRQTB,
DMA
Controller
Command
Status
Serial
Channel
INT
ITS00947
A
B
Channel
Serial
DRQRA,
DRQRB,
DACKA
DACKB
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