參數(shù)資料
型號: SAB82525N
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 4M bps, MULTI PROTOCOL CONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 100/126頁
文件大?。?/td> 730K
代理商: SAB82525N
Semiconductor Group
75
SAB 82525
SAB 82526
SAF 82525
SAF 82526
The following figure gives an example of a DMA driven transmission sequence with a
supposed frame length of 70 bytes, i.e. programmed transmit byte count (XCNT) equal
69 bytes.
Figure 36
DMA Driven Transmission Sequence Example
WR
XCNT
WR
XTF
Transmit Frame (70
Serial
Interface
HSCX
CPU/DMA
Interface
ITD00250
(69)
DRQT(32)
WR
. . .
WR
DRQT(32)
WR
DRQT(6)
WR
32
6
DMA Write Cycles (70)
XPR
. . .
Bytes)
7.5 Data Reception
Interrupt Mode
Also 2
×32 byte FIFO buffers (receive pools) are provided for each channel in receive direction.
There are two different interrupt indications concerned with the reception of data:
– RPF (Receive Pool Full) interrupt, indicating that a 32 byte block of data can be read from
the RFIFO and the received message is not yet complete.
– RME (Receive Message End) interrupt, indicating that the reception of one message is
completed, i.e. either
one message with less than 32 bytes, or the
last part of a message with more than 32 bytes
is stored in the RFIFO.
After an interrupt has been processed, i.e. the received data has been read from the RFIFO,
this must be explicitly acknowledged by the CPU issuing a RMC (Receive Message Complete)
command.
The CPU has to handle the RPF interrupt before additional 32 bytes are received via the serial
interface which would cause a "Receive Data Overflow" condition.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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