參數(shù)資料
型號(hào)： SAA7390
廠商： NXP Semiconductors N.V.
英文描述： High performance Compact Disc-Recordable CD-R controller
中文描述： 高性能式光盤(pán)CD - R光盤(pán)控制器
文件頁(yè)數(shù)： 65/76頁(yè)
文件大?。?/td> 366K
代理商： SAA7390
1996 Jul 02
65
Philips Semiconductors
Preliminary specification
High performance Compact
Disc-Recordable (CD-R) controller
SAA7390
15.8.2
V
DD
= 4.75 to 5.25 V; V
SS
= 0 V; T
amb
=
10 to +70
°
C; unless otherwise specified.
DMA
INTERFACE TIMING
Note
1.
t
CS
+ 30
t
3
and t
CP
; where t
CS
is the synchronization latency and t
CP
is the clock period.
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
DMA read cycle timing;
see Fig.31
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
DACK LOW to DREQ LOW
DACK HIGH to DREQ HIGH
DACK HIGH to DACK LOW
DACK pulse width
DACK LOW to DACK LOW
DACK HIGH to DACK HIGH
DACK LOW to HOSTRD LOW
HOSTRD pulse width
HOSTRD HIGH to DACK HIGH
DACK HIGH to data valid
DACK LOW to data valid
HOSTRD LOW to data valid
DACK HIGH to data release
HOSTRD HIGH to data release
12
35
75
note 1
0
t
12
0
2
2
20
20
30
25
25
25
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DMA write cycle timing;
see Fig.32
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
DACK LOW to DREQ LOW
DACK HIGH to DREQ HIGH
DACK HIGH to DACK LOW
DACK pulse width
DACK LOW to DACK LOW
DACK HIGH to DACK HIGH
DACK LOW to HOSTWR LOW
HOSTWR pulse width
HOSTWR HIGH to DACK HIGH
HOSTWR HIGH to HOSTWR HIGH
data set-up time to HOSTWR HIGH
data hold time from HOSTWR HIGH
data set-up time to DACK HIGH
data hold time from DACK HIGH
12
35
75
note 1
0
30
0
30
8
0
10
10
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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