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1996 Jul 02
35
Philips Semiconductors
Preliminary specification
High performance Compact
Disc-Recordable (CD-R) controller
SAA7390
Table 44
Front-end frame offset: 0xF0E2, F0E3; note 1
Note
1.
This register allows the front-end frame offset counter to be read and reloaded. The counter associated with these
registers is loaded after the most significant byte is written; the least significant byte must be written first to ensure
that the counter is loaded correctly. If a DRAM access is in progress that uses the address from the counter, the
update will be delayed until the access is complete.
Table 45
Front-end offset counter: 0xF09E, 0xF09F; note 1
Note
1.
These registers access the actual counter for the front-end offset counter and therefore change rapidly during a
transfer. The front-end frame offset counter is cleared after reset and after each frame is loaded into the buffer
memory. Therefore, FEFRMOFF should not be loaded during normal operation.
Table 46
Front-end offset counter: 0xF0E4, 0xF0E5; note 1
Note
1.
This register allows the front-end frame number counter to be read and reloaded. The counter associated with these
registers is loaded after the most significant byte is written; the least significant byte must be written first to ensure
that the counter is loaded correctly. If a DRAM access is in progress that uses the address from the counter, the
update will be delayed until the access is completed.
Table 47
Last frame number for storage: 0xF0F8, F0F9; note 1
Note
1.
These registers are used by the buffer manager to set the top of frame storage memory (wrap point). Any memory
past this point is available for general usage by the microcontroller. The outputs of the registers are used directly to
control DRAM access cycles, and will affect any current DRAM cycle in progress.
MNEMONIC
R/W
DATA BYTE
7
6
5
4
3
2
1
0
FEFRMOFF
FEFRMOFF
R/W
R/W
OFFSET7 to OFFSET0
OFFSET11 to OFFSET8
MNEMONIC
R/W
DATA BYTE
7
6
5
4
3
2
1
0
FEOFF
FEOFF
R/W
R/W
OFFSET7 to OFFSET0
OFFSET11 to OFFSET8
MNEMONIC
R/W
DATA BYTE
7
6
5
4
3
2
1
0
FEFRM#
FEFRM#
R/W
R/W
FRAME7
FRAME6
FRAME5
FRAME4
FRAME3
FRAME2
FRAME1
FRAME0
FRAME10 to FRAME8
MNEMONIC
R/W
DATA BYTE
7
6
5
4
3
2
1
0
LASTFRM
LASTFRM
R/W
R/W
FRAME7
FRAME6
FRAME5
FRAME4
FRAME3
FRAME2
FRAME1
FRAME0
FRAME10 to FRAME8