參數(shù)資料
型號(hào)： SAA7390
廠商： NXP Semiconductors N.V.
英文描述： High performance Compact Disc-Recordable CD-R controller
中文描述： 高性能式光盤CD - R光盤控制器
文件頁(yè)數(shù)： 34/76頁(yè)
文件大?。?/td> 366K
代理商： SAA7390
1996 Jul 02
34
Philips Semiconductors
Preliminary specification
High performance Compact
Disc-Recordable (CD-R) controller
SAA7390
11 BUFFER MANAGER
11.1
Front-end to buffer manager interface
The buffer manager interface to the front-end is write only
with no handshaking. The front-end passes one byte of
data and a write strobe to the buffer manager; this byte will
be one of five types of data (see Table 44). The data byte
is latched and the interface is given the highest priority
thus no wait signal is required. The other signals passed
from the front-end logic are an end-of-frame strobe (which
is the same as the status byte write strobe), a
software-generated reset pulse (used to reset the
front-end counters), and a reset pulse for the Q-channel
and sub-code offset counters.
The buffer manager provides the remainder of the logic to
write the data into the RAM and keep track of the frame
addresses and offset addresses. This logic consists of a
12-bit frame offset counter FEOFF, for data and an 11-bit
frame counter; this is a relative frame number and is not
related to the CD-ROM frame number. Offset counters are
also provided for the four other types of data. The other
offset address generators are based on fixed addresses,
and they will be loaded with the start address at the
beginning of each frame. The five types of data from the
front-end are loaded into the frame map as shown in
Table 44.
Table 43
Data types from the front-end
START
END
LENGTH
DATA TYPE
0x000
0x930
0x940
0x9A0
0xBDE
0x92F
0x93F
0x99F
0xAC5
0xBDE
0x930
0x010
0x060
0x126
0x001
header, data and parity
Q-channel
sub-channel
error flags
status byte
Initially the front-end frame counter and all of the offset
counters are cleared by reset or loaded with the contents
of FEFRM# when the last frame as specified by LASTFRM
is filled; therefore FEFRM# should be loaded with the
required starting frame number. FEFRM# will load the
counter immediately if FEWBLK from BMFECTL is clear.
If TDB_EN in BMFECLT is set then one frame may be read
multiple times from memory; TDB selects the frame to be
read and TDB_CNT determines the number of times the
frame will be repeated. When this process is active, the
frame counter will not increment until TDB_CNT reaches
zero.
LASTFRM establishes the limit of the frame memory. This
register should be loaded with the required number of
frames; the amount of memory used is 3 kbytes times the
number of frames. The front-end frame address counter
uses this value to determine the correct location to re-load
the counter to the starting frame number, FEFRM#.
The frame counter and the frame data offset counter may
be loaded by the microcontroller; this allows the starting
frame number (via FEFRM#) to be modified by the
microcontroller, and the frame data offset counter
(FEFRMOFF) may be loaded for test purposes.
Once the data load process starts, the offset counter
(FEOFF) increments after each byte is written into
memory. This process continues until an end-of-frame
signal is received from the front-end logic. If an error
occurs and the offset counter increments past the
maximum 2352, an interrupt will be issued to the
microcontroller.
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