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參數(shù)資料
| 型號(hào)： | SAA7390 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | High performance Compact Disc-Recordable CD-R controller |
| 中文描述： | 高性能式光盤CD - R光盤控制器 |
| 文件頁數(shù)： | 27/76頁 |
| 文件大?。?/td> | 366K |
| 代理商： | SAA7390 |
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1996 Jul 02
27
Philips Semiconductors
Preliminary specification
High performance Compact
Disc-Recordable (CD-R) controller
SAA7390
Table 25
Baud rate generator control: 0xF0C0; note 1
Note
1.
Register 0xF0C0 controls the S2B UART baud rate and selective inversion of the sub-code information. Control over
the parity and the clock doubler is also included together with the ability to invert the sub-code and Q-channel
information.
Table 26
BRGSEL field descriptions
9.2
SPI UART registers
This section describes the registers used for SPI control.
Table 27
Serial communication control: 0xF0F1; note 1
Note
1.
Register 0xF0F1 selects and reports the signals and edges of interrupts required to control the basic engine.
The least significant four bits perform the selection and are read/write. If both the rising and falling edges are set then
both signal edges cause interrupts. If both rising and falling edges are cleared then neither edge will cause an
interrupt. The most significant four bits report which edge of which signal caused the interrupt and are read-only; the
interrupt generated by these bits is cleared by reading register 0xF0F1.
MNEMONIC
R/W
DATA BYTE
7
6
5
4
3
2
1
0
BRGSEL
R/W
C_34_16
LOCK
EVENPAR INVSUBC
INVQ
S2BSEL1
S2BSEL0
FIELD
LOGIC
DESCRIPTION
S2BSEL1 and S2BSEL0
00
01
10
11
31.25 kbaud transfer rate
62.5 kbaud transfer rate
187.5 kbaud transfer rate
not specified
inverts all Q-channel information if set
inverts all sub-code information if set
selects even parity for S2B UART is set
read only information; indicates clock synthesizer is stable (after reset) and it is
ready to set C_34_16
once LOCK is HIGH, asserting this bit engages the clock doubler
INVQ
INVSUBC
EVENPAR
LOCK
C_34_16
MNEMONIC
R/W
DATA BYTE
7
6
5
4
3
2
1
0
SC_CTL
R/W
SSU_REP SSD_REP CSU_REP CSD_REP SSU_SEL SSD_SEL CSU_SEL CSD_SEL
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