參數(shù)資料
型號： SAA7390
廠商： NXP Semiconductors N.V.
英文描述： High performance Compact Disc-Recordable CD-R controller
中文描述： 高性能式光盤CD - R光盤控制器
文件頁數(shù)： 32/76頁
文件大?。?/td> 366K
代理商： SAA7390
1996 Jul 02
32
Philips Semiconductors
Preliminary specification
High performance Compact
Disc-Recordable (CD-R) controller
SAA7390
10.2
Front-end status and control
Table 39
Front-end control: 0xF0BB; note 1
Note
1.
Register 0xF0BB controls the front-end of the SAA7390. The naming convention used here is similar to that used in
the block decoders.
Table 40
FECTL field descriptions
MNEMONIC
R/W
DATA BYTE
7
6
5
4
3
2
1
0
FECTL
R/W
SIM_EOF
RSMD
BREAK
RWMD
ENABRED AUDMODE SYNASYN
ECMD
FIELD
LOGIC
DESCRIPTION
ECMD
0
Data is shifted in and stored when the next synchronization pattern is detected;
(SYNASYN = 1 and AUDMODE = 0).
Data flow stop just before next synchronization pattern. ECMD is set on a reset condition;
(SYNASYN = 1).
Synchronous/asynchronous selection; this controls the method by which data is started and
stopped by the block decoder, only operates in data mode.
Causes a ‘panic stop’. A partial frame will reside in current and subsequent buffers unless
SIM_EOF is set then cleared; (ECMD = 1).
Data is started and stopped on frame boundaries (on synchronization patterns).
Data mode. Cleared on reset.
Audio mode, where the bit clock is shifted to accommodate EIAJ format. HQRDY in
INTRFLG follows HDRRDY in data mode and QFRMDRY in audio mode.
Enable red book to data path; while in audio mode, this is equivalent to ECMD in the data
mode. No asynchronous stop is provided in the audio mode.
Data flow will stop when the next F1 C-flag is detected. Cleared on a reset condition.
Red book data is input to buffer after the detection of the next F1 C-flag.
This must be pulsed HIGH then LOW every 212 ms to prevent the watch-dog timer from
resetting the SAA7390 and the drive. The length of the reset pulse is 967
μ
s. If RWMD is set,
the watch-dog timer is disabled.
When set, the S2B UART transmitter output is held HIGH.
When the pulse is HIGH then LOW, the block decoder begins to search for a synchronization
pattern in the data bitstream. Once a synchronization pattern is found, MODE, MINS, SECS,
and FRMS become valid.
This provides a firmware reset to the frame sequencer and parts of the buffer manager.
This would be required if an asynchronous stop of the data stream occurs. Pulsing this HIGH
then LOW resets all counters and establishes a ‘beginning of frame’ state. DCOACT in
RDDSTAT must be LOW to allow SIM_EOF to have any effect. If SIM_EOF is set, no data or
sub-code is stored in the buffer.
1
SYNASYN
0
1
0
1
AUDMODE
ENABRED
0
1
RWMD
BREAK
RSMD
SIM_EOF
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