參數(shù)資料
型號(hào)： SAA7390
廠商： NXP Semiconductors N.V.
英文描述： High performance Compact Disc-Recordable CD-R controller
中文描述： 高性能式光盤CD - R光盤控制器
文件頁數(shù)： 29/76頁
文件大?。?/td> 366K
代理商： SAA7390
1996 Jul 02
29
Philips Semiconductors
Preliminary specification
High performance Compact
Disc-Recordable (CD-R) controller
SAA7390
Table 31
Track descriptor block address: 0xF096 and 0xF097; note 1
Note
1.
Registers 0xF096 and 0xF097 contain the frame address of the TDB. When the buffer manager frame count equals
the contents of this register and the TDB_EN bit is set in BMFECTL, the frame counter will not be allowed to
increment until TDB_CNT equals zero.
9.4
Miscellaneous control registers
Table 32
Host interface direction and audio mode control: 0xF0C1; note 1
Note
1.
Register 0xF0C1 controls the data path to the host interface and some audio functions.
Table 33
WTDIR field descriptions
MNEMONIC
R/W
DATA BYTE
7
6
5
4
3
2
1
0
TDB
TDB
R/W
R/W
TDB address 7 to TDB address 0
TDB address 10 to 8
MNEMONIC
R/W
DATA BYTE
7
6
5
4
3
2
1
0
WTDIR
R/W
CBSB
OVER4X
BSB
HOSTDIR AUTOSTR
FIELD
DESCRIPTION
AUTOSTR
Automatic store; default is off. When set HIGH, the front-end will automatically begin storing data or
audio when the contents of the header/Q-channel registers equals the contents of the STRTMIN,
STRTSEC and STRTFRM registers. If a header/Q-channel error occurs to invalidate the address,
auto-store is inhibited. Storing of data will continue until the contents of the STOPCNT equals zero, at
which time it will automatically stop.
Host direction; default LOW. This selects the microcontroller data path to the SCSI interface. Setting
this HIGH selects the buffer managers DMA path. When using a 53CF92A, this should be set and left
HIGH since the microcontroller has a separate command path into the 53CF92A whereas the
53CF90B requires the buffer manager and microcontroller to share the same path.
Byte swap bit. Defaults to swapping the most significant byte and least significant byte in the audio
mode such that the least significant byte of all audio samples is stored at even addresses in the
DRAM. Setting this HIGH causes the audio data to be stored in the same way as in the data mode.
4
×
over-sampling bit selection; default LOW select transmit, or no over-sampling, mode for the
sub-code and C-flag UARTs. Setting this bit HIGH will cause the sub-code and C-flag data to be
sampled at one quarter the data rate allowing Q-channel information to be correctly stored in the
registers while the CD-60 is outputting audio data at 4
×
over-sampling.
CBD2 byte swap bit; default LOW allows data from the DRAM buffer to be sent to the CDB2 normally
(data mode). When set HIGH, the high byte and low byte are swapped since data from the host will be
swapped. As a result, Red book in the bypass mode will be correctly aligned.
HOSTDIR
BSB
OVER4X
CBSB
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