參數(shù)資料
型號(hào)： SAA7390
廠商： NXP Semiconductors N.V.
英文描述： High performance Compact Disc-Recordable CD-R controller
中文描述： 高性能式光盤CD - R光盤控制器
文件頁(yè)數(shù)： 50/76頁(yè)
文件大小： 366K
代理商： SAA7390
1996 Jul 02
50
Philips Semiconductors
Preliminary specification
High performance Compact
Disc-Recordable (CD-R) controller
SAA7390
F0B7
F0B9
F0BA
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F0BC
F0BD
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F0BF
F0C0
F0C1
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F0C9
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F0E5
HOSTPASS
WTGCTL
RDSW
FECTL
HOSTPASS
HOSTPASS
HOSTPASS
HOSTPASS
BRGSEL
WTDIR
GPIOCTL
RDDSTAT
SERCOM
STRTMIN
STRTSEC
STOPCNT
STRTFRM
STOPCNT
RDJMPRS
CMSK
QINDX
CCMD
CSTS
CBCH
CBCL
CMIN
CSEC
CFRM
CTST
CCTL
CSTAT
CMDE
CFN
CCHAN
CSMD
CDTB
BMFECTL
FEFRMOFF
FEFRMOFF
FEFRM#
FEFRM#
R/W
W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
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R/W
R/W
R/W
R/W
R
R/W
R
R/W
R
R/W
R/W
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W
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R
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R/W
R/W
R/W
R/W
R/W
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R/W
R/W
R/W
interface device pass through register address 0x0B
GLIC control registers (audio control)
drive control switches register
front-end control register
interface device pass through register address 0x0C
interface device pass through register address 0x0D
interface device pass through register address 0x0E
interface device pass through register address 0x0F
baud rate generator select register
SAA7390-host interface direction plus audio mode control
general purpose bits control register
data status register
SAA7390: basic engine communications port
start minutes (automatic control)
start seconds (automatic control)
stop count low byte (automatic control)
start frame (automatic control)
stop count high byte (automatic control)
option jumper register (attached to DRAM data bus)
CDB2 interrupt mask register
Q channel index (track relative)
CDB2 command register
CDB2 status register
CDB2 block counter high
CDB2 block counter low
CDB2 header minutes register
CDB2 header seconds register
CDB2 header frame register
test register for CDB2 block
control register for CDB2 block
status register for CDB2 block
CDB2 header mode register
CDB2 file number register
CDB2 channel number register
CDB2 sub-mode byte register
CDB2 data type byte register
buffer manager front-end control
front-end 8 LSBs; frame offset
front-end 4 MSBs; frame offset (bit 0 to bit 3)
front-end 8 LSBs of the frame
front-end 3 MSBs of the frame (bit 0 to bit 2)
ADDRESS
MNEMONIC
READ/WRITE
DESCRIPTION
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