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參數(shù)資料
| 型號(hào)： | S1C62740D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC109 |
| 封裝： | DIE-109 |
| 文件頁(yè)數(shù)： | 8/249頁(yè) |
| 文件大?。?/td> | 1712K |
| 代理商： | S1C62740D |
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S1C62740 TECHNICAL HARDWARE
EPSON
I-93
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
(3) Wait time for A/D conversion
To perform a stable A/D conversion, the following wait times are
necessary.
In the case of voltage measurement mode and differential voltage
measurement mode
Take 300 msec or more wait time from the beginning of the refer-
ence voltage VR1 generation or impressing from outside to the end
of an input integration period. (Satisfy the regulation time by
delaying the timing of the A/D converter ON.)
Resistance measurement mode
Take a time that is calculated by the following expression or more
from turning the A/D converter ON to the end of the input integra-
tion period. (The A/D converted data until the calculated time has
passed is invalid.)
10
× 0.1 F (capacitance for VR, -VR generation circuit) × R (Rref + 130 k)
(4) Reading of the A/D conversion result
The dual slope counter is a 13-bit binary counter and is counted
up from "0" to the reverse integration period. The result that has
been counted is latched upon completion of the reverse integration
period and the data from that latch can be read. This data AD0–
AD12 is allocated to the address F7H–FAH. The register ADP that
indicates the polarity of the analog input voltage is allocated to
FAH, in addition to the AD12 (MSB of the data).
When the analog input is positive (+) the ADP becomes "1" and
when it is negative (-) it becomes "0".
The latched data is effective until the next A/D conversion is
completed and it is necessary to read up to that point. Basically
you should process the read processing by the A/D interrupt.
Moreover, you should read the data in order of F7H
→ F8H → F9H
→ FAH from the lower side. This is due to the following reason.
When the following A/D conversion terminates during data read-
ing, the latched data is just rewritten. For this reason, the IDR bit
is set into the address FBH, so that it can decide whether the data
read is effective or invalid, by reading the IDR bit following the
reading of data. When the reading of the data in the above se-
quence has been completed prior to the termination of the next A/
D conversion, the IDR becomes "0", indicating that the data is
effective. When the following A/D conversion has been terminated
and the latch rewritten before the reading terminates, the IDR
becomes "1", indicating that the data is invalid.
The circuit that sets this IDR decides whether the data has been
read and the reading terminated by the above mentioned data read
address. Consequently, you should read the data in the above
mentioned sequence and then decide whether the data is effective
or invalid by reading the IDR.
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