- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄98068 > S1C62740D 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC109 PDF資料下載
參數(shù)資料
| 型號(hào)： | S1C62740D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC109 |
| 封裝： | DIE-109 |
| 文件頁(yè)數(shù)： | 135/249頁(yè) |
| 文件大?。?/td> | 1712K |
| 代理商： | S1C62740D |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)當(dāng)前第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)
I-10
EPSON
S1C62740 TECHNICAL HARDWARE
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
Initial reset can be executed externally by setting the reset terminal
to the low level.
Maintain a low level of 0.1 msec to securely perform the initial reset.
When the reset terminal goes high, the CPU begins to operate.
However, when turning the power on, the reset terminal should be
set at a low level as in the timing shown in Figure 2.2.2.
Reset terminal
(RESET)
VDD
RESET
2.0 msec or more
2.2 V
0.4VDD
0.1VDD or less (low level)
Power on
Fig. 2.2.2
Initial reset at power on
The reset terminal should be set to 0.1VDD or less (low level) until
the supply voltage becomes 2.2 V or more.
After that, a level of 0.4VDD or less should be maintained more
than 2.0 msec.
Another way of executing initial reset externally is to input a low
signal simultaneously to the input ports (K00–K03) selected with
the mask option.
Since this initial reset signal passes through the noise reject
circuit, simultaneous low input of 0.4 msec or less is considered as
noise. Maintain the specified input port terminals at a low level of
1.5 msec (when the oscillation frequency fOSC1 = 32 kHz) to se-
curely perform the initial reset.
Table 2.2.1 shows the combinations of input ports (K00–K03) that
can be selected with the mask option.
Simultaneous low
input to terminals
K00–K03
Table 2.2.1
Combinations of input ports
A
Not use
B
K00*K01
C
K00*K01*K02
D
K00*K01*K02*K03
When, for instance, mask option D (K00*K01*K02*K03) is selected,
initial reset is executed when the signals input to the four ports
K00–K03 are all low at the same time. The initial reset is done,
even when a key entry including a combination of selected input
ports is made.
Further, the time authorize circuit can be selected with the mask
option. The time authorize circuit performs initial reset, when the
input time of the simultaneous low input is authorized and found
to be the same or more than the defined time (1 to 2 sec). Since
clock timer output is used for time authorization, when the clock
timer is reset during time authorization, the authorization time is
also reduced. (The shortest is 0.5 msec due to the noise reject
circuit.)
In the SLEEP status, the noise reject circuit and the time authorize
circuit are bypassed since the OSC1 oscillation circuit is off.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S1C62920D | 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC63 |
| S1C62A33D | 4-BIT, MROM, 0.6 MHz, MICROCONTROLLER, UUC86 |
| S1C62N82F | 4-BIT, MROM, 0.032 MHz, MICROCONTROLLER, PQFP80 |
| S1C63158F0A0100 | 4-BIT, FLASH, 4.2 MHz, MICROCONTROLLER, PQFP100 |
| S1C63358F0A0100 | 4-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S1C63004 | 制造商:EPSON 制造商全稱:EPSON 功能描述:CMOS 4-bit Single Chip Microcontroller |
| S1C63008 | 制造商:EPSON 制造商全稱:EPSON 功能描述:CMOS 4-bit Single Chip Microcontroller |
| S1C63016 | 制造商:EPSON 制造商全稱:EPSON 功能描述:CMOS 4-bit Single Chip Microcontroller |
| S1C63158 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C63408 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。