
II-50
EPSON
S1C62740 TECHNICAL SOFTWARE
CHAPTER 6: PERIPHERAL CIRCUITS (Serial Interface Circuit)
Master/slave mode and synchronous clock (SCLK)
The serial interface of the S1C62740 has two types of operation
mode: master mode and slave mode.
In the master mode, it uses an internal clock as synchronous
clock. In the slave mode, the synchronous clock output from the
external (master side) serial device is input.
The master mode and slave mode are selected through registers
SCS0 and SCS1; when the master mode is selected, a synchronous
clock may be selected from among 3 types as shown in Table
6.10.2.
Table 6.10.2
Synchronous clock selection
At initial reset, the slave mode (external clock mode) is selected.
Moreover, the synchronous clock, along with the input/output of
the 8 bits serial data, is controlled as follows:
–
At master mode, after output of 8 clocks from the SCLK (P22)
terminal, clock output is automatically suspended and SCLK
(P22) terminal is fixed at high level.
–
At slave mode, after input of 8 clocks to the SCLK (P22) termi-
nal, subsequent clock inputs are masked.
–
When using PTOVF signal selection, the synchronous clock is
equal to [PT input predivided frequency / (PT reload register
× 2)].
Serial data output
By setting the parallel data to data registers SD0–SD3 and SD4–
SD7 individually and writing "1" to SCTRG (DCHD0), it synchro-
nizes with the synchronous clock and serial data is output at the
SOUT (P21) terminal.
When the output of the 8 bits data from SD0–SD7 is completed, the
interrupt factor flag ISIO is set to "1" and interrupt is generated.
Moreover, the interrupt can be masked by the interrupt mask
register EISIO. Note, however, that regardless of the setting of the
interrupt mask register, the interrupt factor flag is set to "1" after
output of the 8 bits data.
Serial data input
By writing "1" to SCTRG, the serial data is input from the SIN (P20)
terminal, synchronizes with the synchronous clock, and is
sequentially read in the 8 bits shift register.
SCS1
SCS0
Mode
Synchronous clock
1
CLK
1
0
Master mode
CLK/2
0
1
PTOVF
0
Slave mode
External clock
CLK:
CPU system clock
PTOVF: Programmable timer overflow signal