
S1C62740 TECHNICAL HARDWARE
EPSON
I-53
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
Control of clock
timer
Table 4.8.1 shows the clock timer control bits and their addresses.
Table 4.8.1 Control bits of clock timer
*1 Initial value at the time of initial reset
*5 Constantly "0" when being read
*2 Not set in the circuit
*6 Refer to main manual
*3 Undefined
*7 Page switching in I/O memory is not necessary
*4 Reset (0) immediately after being read
Address
Comment
Register
D3
D2
D1
D0
Name
Init
1
0
*1
C6H
IT32
R
IT1
IT2
IT8
IT32
0
Interrupt factor flag (clock timer 1 Hz)
Interrupt factor flag (clock timer 2 Hz)
Interrupt factor flag (clock timer 8 Hz)
Interrupt factor flag (clock timer 32 Hz)
Yes
No
IT8
IT2
IT1
*4
*7
CCH
EIT32
EIT1
EIT2
EIT8
EIT32
0
Enable
Mask
EIT8
EIT2
EIT1
R/W
Interrupt mask register (clock timer 1 Hz)
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
E2H
TMRST
W
0
TMRST
Reset
–
0
–
*2
*5
TM0
R
TM3
TM2
TM1
TM0
–
TM1
TM2
TM3
E3H
*3
Unused
Clock timer and watchdog timer reset
Clock timer data (16 Hz)
Clock timer data (32 Hz)
Clock timer data (64 Hz)
Clock timer data (128 Hz)
R
TM4
R
TM7
TM6
TM5
TM4
–
TM5
TM6
TM7
E4H
*3
Clock timer data (1 Hz)
Clock timer data (2 Hz)
Clock timer data (4 Hz)
Clock timer data (8 Hz)
TM0–TM7:
Timer data
(E3H, E4H)
The 128 Hz–1 Hz timer data of the clock timer can be read out with
these registers. These eight bits are read only, and writing opera-
tions are invalid.
At initial reset, the timer data is initialized to "00H".
EIT32, EIT8, EIT2, EIT1:
Interrupt mask register
(CCH)
These registers are used to select whether to mask the clock timer
interrupt.
When "1" is written: Enabled
When "0" is written: Masked
Reading: Valid
The interrupt mask registers (EIT32, EIT8, EIT2, EIT1) are used to
select whether to mask the interrupt to the separate frequencies
(32 Hz, 8 Hz, 2 Hz, 1 Hz).
Writing to the interrupt mask registers can be done only in the DI
status (interrupt flag = "0").
At initial reset, these registers are all set to "0".