I-104
EPSON
S1C62740 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit)
To obtain a stable SVD detection result, the SVD circuit must be
on for at least l00 sec. So, to obtain the SVD detection result,
follow the programming sequence below.
Set SVDON to "1"
Maintain for 100 sec minimum
Set SVDON to "0"
Read SVDDT
However, when fOSC1 is selected for CPU system clock, the instruc-
tion cycles are long enough, so there is no need to worry about
maintaining 100 sec for SVDON = "1" in the software.
When SVD is on, the IC draws a large current, so keep SVD off
unless it is.
Control of SVD
circuit
Table 4.14.2 shows the control bits and their addresses for the
SVD circuit.
Table 4.14.2 Control bits for SVD circuit
*1 Initial value at the time of initial reset
*5 Constantly "0" when being read
*2 Not set in the circuit
*6 Refer to main manual
*3 Undefined
*7 Page switching in I/O memory is not necessary
*4 Reset (0) immediately after being read
SVDS0, SVDS1:
SVD criteria voltage setting
(FFHD2, D3)
Criteria voltage for SVD is set as shown in Table 4.14.3.
SVD1
SVD0
Criteria voltage
0
2.6 V
0
1
2.5 V
1
0
2.4 V
1
2.3 V
Table 4.14.3
Criteria voltage setting
At initial reset, these registers are set to "0".
SVDON:
SVD ON/OFF
(FFHD0)
Turns the SVD circuit ON and OFF.
When "1" is written: SVD circuit ON
When "0" is written: SVD circuit OFF
Reading: Valid
When SVDON is set to "1", source voltage detection by the SVD
circuit is executed. As soon as SVDON is reset to "0", the result is
loaded to in the SVDDT register. To obtain a stable SVD detection
result, the SVD circuit must be on for at least l00 sec.
At initial reset, this register is set to "0".
Address
Comment
Register
D3
D2
D1
D0
Name
Init
1
0
*1
*7
FFH
SVDON
SVDS1
SVDS0
SCDDT
SCDON
0
Low
On
Normal
Off
SVDDT
SVDS0
SVDS1
R/W
SVD criteria voltage setting
0: 2.6 V, 1: 2.5 V, 2: 2.4 V, 3: 2.3 V
Supply voltage evaluation data
SVD circuit On/Off
RR/W