
S1C62740 TECHNICAL SOFTWARE
EPSON
II-57
CHAPTER 6: PERIPHERAL CIRCUITS (SVD Circuit)
SVD (Supply Voltage Detection) Circuit
6.12
I/O data memory of
the SVD circuit
The control registers of the SVD circuit are shown in Table 6.12.1.
Table 6.12.1 Control registers of SVD circuit
*1 Initial value at the time of initial reset
*5 Constantly "0" when being read
*2 Not set in the circuit
*6 Refer to main manual
*3 Undefined
*7 Page switching in I/O memory is not necessary
*4 Reset (0) immediately after being read
Control of the SVD
circuit
The S1C62740 has a built-in SVD (supply voltage detection) circuit
which allows detection of power voltage drop through software.
Turning the SVD operation on and off can be controlled through
the software (SVDON: FFHD0). Because the IC consumes a large
amount of current during SVD operation, it is recommended that
the SVD operation be kept OFF unless it is otherwise necessary.
Also, the SVD criteria voltage can be set by software. The criteria
voltage can be set by SVDS1 and SVDS0 (FFHD3, D2) as follows:
When SVDON is set to "1", SVD detection is executed. As soon as
SVDON is set to "0" the detection result is loaded to the SVDDT
register. To obtain a stable result, the SVD circuit must be set to
ON with at least 100 sec. Hence, to obtain the SVD detection
result, follow the programming sequence below.
1. Set SVDON to "1" (ON)
2. Maintain at least 100 sec minimum
3. Set SVDON to "0" (OFF)
4. Read out SVDDT
However, when a crystal oscillation clock (fOSC1) is selected for CPU
system clock, the instruction cycle are long enough, so that there
is no need for concern about maintaining 100 sec for the SVDON
= "1" with the software.
SVDS1
SVDS0
Criteria voltage
0
2.6 V
0
1
2.5 V
1
0
2.4 V
1
2.3 V
Table 6.12.2
Criteria voltage selection
Address
Comment
Register
D3
D2
D1
D0
Name
Init
1
0
*1
*7
FFH
SVDON
SVDS1
SVDS0
SCDDT
SCDON
0
Low
On
Normal
Off
SVDDT
SVDS0
SVDS1
R/W
SVD criteria voltage setting
0: 2.6 V, 1: 2.5 V, 2: 2.4 V, 3: 2.3 V
Supply voltage evaluation data
SVD circuit On/Off
R
R/W