
S1C62740 TECHNICAL SOFTWARE
EPSON
II-65
CHAPTER 6: PERIPHERAL CIRCUITS (Sleep)
Sleep
6.14
I/O data memory of
sleep function
The control registers of the sleep function are shown in Table
6.14.1.
Table 6.14.1 Control registers of sleep function
Control of the sleep
function
The S1C62740 has a sleep function. When it executes "SLP"
instruction, then it sleeps. In the SLEEP mode, the core and all
peripheral circuit are not working except the K10 input port and
external system reset circuits. During the chip is sleeping, all
RAM's data and I/O registers remain the same values. Because all
output registers (like R00–R03, P00–P03, etc.) are keeping the
same values. So before the chip go to sleep first turn on or turn off
the necessary output pins.
When shifting to the SLEEP mode, the CPU clock must be set to
OSC1 and the OSC3 oscillation circuit must be off.
The K10 input port and external system reset circuit are use to
wakeup the S1C62740 chip while it is sleeping.
Use external system reset to wakeup
Set the proper RAM's data and I/O register's data if necessary.
Executes "SLP" and the chip sleeps.
Low input to external system reset pin.
Hardware initial I/O registers as default values, and the pro-
gram counter go to 100H.
Software initialize same procedures according the application
necessaries.
*1 Initial value at the time of initial reset
*5 Constantly "0" when being read
*2 Not set in the circuit
*6 Refer to main manual
*3 Undefined
*7 Page switching in I/O memory is not necessary
*4 Reset (0) immediately after being read
Address
Comment
Register
D3
D2
D1
D0
Name
Init
1
0
*1
C2H
IK1
R
0
IK1
Yes
No
0
–
0
*2
*5
*4
C9H
EIK0
0
EIK1
EIK0
–
0
Unused
Interrupt mask register (K10)
Interrupt mask register (K00–K03)
Enable
Mask
EIK1
0
*2
*5
*7
R/W
Unused
Interrupt factor flag (K10)
R
DFK10
R
0
DFK10
–
1
0
D3H
*2
*5
Unused
Input comparison register (K10)
R/W
DFH
OSCC
0
CLKCHG
OSCC
–
0
OSC3
On
OSC1
Off
CLKCHG
0
*5
R/W
Unused
CPU system clock switch
OSC3 oscillation On/Off
*2
R