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參數(shù)資料
| 型號(hào)： | S1C62740D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC109 |
| 封裝： | DIE-109 |
| 文件頁(yè)數(shù)： | 7/249頁(yè) |
| 文件大?。?/td> | 1712K |
| 代理商： | S1C62740D |
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I-92
EPSON
S1C62740 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (A/D Converter)
Here we will explain about the control and interrupt of the A/D
conversion and reading of data.
Before beginning A/D conversion, it is necessary to set the analog
input terminal and measurement items explained previously and
set the reference voltage generation circuit and middle electric
potential generation circuit.
A/D conversion and
interrupt
(1) Turning A/D converter ON/OFF
The power supply to the circuit of the A/D converter is normally
kept OFF, in order to reduce current consumption. The A/D
converter starts when "1" is written into the register ADON and
continues to operate until a "0" has been written. It terminates A/D
conversion when a "0" has been written into the ADON and the
circuit also goes OFF.
The ADON can be read and is "1" while the circuit is operating and
is "0" when it is stopped.
When "1" is written into the ADON, it resets the dual slope counter
to "0" and executes the A/D conversion sequence from auto zero
adjustment. Writing "1" into ADON is also effective during A/D
conversion and it terminates the sequence during the current
execution and starts a new A/D conversion sequence.
ADON write signal
ADON register
A/D converter circuit
Integral AMP output
11
0
ON
Reset
Fig. 4.12.16
Control of A/D conversion by the
ADON register
A/D interrupt
When it terminates the integration of the analog input and starts
the reverse integration according to the reference voltage, the dual
slope counter is counted up from "0". At the point where the
integral AMP output due to the reverse integration has crossed "0",
the count stops and the data of the dual slope counter is latched.
When the reverse integration period has terminates, the A/D
interrupt factor flag IAD is set to "1" and an interrupt occurs.
The A/D interrupt can also be masked by writing a "0" into the
interrupt mask register EIAD. When EIAD is set to "1", an interrupt
occurs.
The interrupt factor flag IAD is set to "1" when the reverse integra-
tion period has terminates, regardless of the setting of the interrupt
mask register and is reset to "0" by reading.
(2)
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