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參數(shù)資料
| 型號： | S1C60N04D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC48 |
| 封裝： | DIE-48 |
| 文件頁數(shù)： | 29/50頁 |
| 文件大?。?/td> | 372K |
| 代理商： | S1C60N04D |
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S1C60N04 TECHNICAL MANUAL
EPSON
29
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP)
HALT and SLEEP modes
When the HALT instruction is executed, the CPU stops operating and enters the HALT mode. The
oscillation circuit and the peripheral circuits operate in the HALT mode. By an interrupt, the CPU exits
the HALT mode and resumes operating.
Executing the SLP instruction set the IC in the SLEEP mode that stops operations of the CPU and oscilla-
tion circuit. The SLEEP mode will be canceled by an input interrupt request from the input port K00–K03.
Consequently, at least one input port (K00, K01, K02 or K03) interrupt must be enabled before shifting to
the SLEEP status. When the SLEEP status is canceled by a K0n input interrupt, the CPU waits for oscilla-
tion to stabilize then restarts operating.
Refer to the "S1C6200/6200A Core CPU Manual" for transition to the HALT/SLEEP status and timing of
its cancellation.
Figures 4.8.2, 4.8.3 and 4.8.4 show the sequence to enter and cancel the SLEEP mode, respectively.
Program counter
USLP (controlled by software
command "SLP")
CLK
K input
Interrupt mask register
PC
PC+1
PC+2
PC+3
PC+4
Fig. 4.8.2 Entering SLEEP mode
Program counter
USLP (controlled by software
command "SLP")
CLK
K input
Interrupt mask register
PC+4
104H
PC+4
PC+5
Waiting for clock stabilization
Execute K-input interrupt service routine
Key interrupt vector
Interrupt service routine
start address
Interrupt service routine
end address
Fig. 4.8.3 Wakeup from SLEEP mode by K-input
Program counter
USLP (controlled by software
command "SLP")
CLK
RESET input
Interrupt mask register
PC+4
100H
101H
102H
103H
Fig. 4.8.4 Wakeup from SLEEP mode by RESET pad
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