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參數資料
| 型號： | S1C60N04D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC48 |
| 封裝： | DIE-48 |
| 文件頁數： | 22/50頁 |
| 文件大?。?/td> | 372K |
| 代理商： | S1C60N04D |
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S1C60N04 TECHNICAL MANUAL
EPSON
23
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
4.6.2 Mask option
(1) Segment allocation
As shown in Figure 4.l.1, the S1C60N04 display data is decided by the data written to the display
memory (write-only) at address 090H–0AFH.
The address and bits of the display memory can be made to correspond to the segment pins (SEG0–
SEG25) in any combination through mask option. This simplifies design by increasing the degree of
freedom with which the liquid crystal panel can be designed.
Figure 4.6.2.1 shows an example of the relationship between the LCD segments (on the panel) and the
display memory in the case of 1/3 duty.
aa'
f
f'
g'
g
ee'
d
d'
p'
p
c'
b'
b
c
SEG10
SEG11
SEG12
Common 0
Common 1
Common 2
09AH
09BH
09CH
09DH
Address
d
p
d'
p'
D3
c
g
c'
g'
D2
b
f
b'
f'
D1
a
e
a'
e'
D0
Data
Display data memory allocation
SEG10
SEG11
SEG12
9A, D0
(a)
9A, D1
(b)
9D, D1
(f')
9B, D1
(f)
9B, D2
(g)
9A, D2
(c)
9B, D0
(e)
9A, D3
(d)
9B, D3
(p)
Pin address allocation
Common 0
Common 1
Common 2
Fig. 4.6.2.1 Segment allocation
(2) Drive duty
According to the mask option, either 1/4, 1/3 or 1/2 duty can be selected as the LCD drive duty.
Table 4.6.2.1 shows the differences in the number of segments according to the selected duty.
Table 4.6.2.1 Differences according to selected duty
Duty
1/4
1/3
1/2
COM used
COM0–COM3
COM0–COM2
COM0–COM1
Max. number of segments
104 (26
× 4)
78 (26
× 3)
52 (26
× 2)
Frame frequency *
30.5 Hz
40.7 Hz
30.5 Hz
When fOSC = 2 MHz, tolerance is within 5%
(3) Output specification
The segment pins (SEG0–SEG25) are selected by mask option in pairs for either segment signal output
or DC output (VDD and VSS binary output). When DC output is selected, the data corresponding to
COM0 of each segment pin is output.
When DC output is selected, either complementary output or Pch open drain output can be selected
for each pin by mask option.
Note: The pin pairs are the combination of SEG (2
n) and SEG (2n + 1) (where n is an integer from 0 to 12).
(4) Drive bias
For the drive bias of the S1C60N04, either 1/3 bias or 1/2 bias can be selected by the mask option.
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