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參數(shù)資料
| 型號： | S1C60N04D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC48 |
| 封裝： | DIE-48 |
| 文件頁數(shù)： | 2/50頁 |
| 文件大?。?/td> | 372K |
| 代理商： | S1C60N04D |
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4
EPSON
S1C60N04 TECHNICAL MANUAL
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
CHAPTER
2POWER SUPPLY AND INITIAL RESET
2.1 Power Supply
With a single external power supply (
) supplied to VDD through VSS, the S1C60N04 generates the
necessary internal voltages with the power divider.
Supply voltage: 2.7 to 3.6 V or 4.5 V to 5.5 V
The power divider generates the LCD drive voltages <VL1, VL2> by dividing the supply voltage as shown
in Figure 2.1.1.
The circuit configuration is set according to the LCD drive bias selection with a mask option.
When 1/3 bias is selected, the supply voltage is divided by 3 to generate VL1 and VL2.
When 1/2 bias is selected, the supply voltage is divided by 2 and VL1 and VL2 is shorted internally.
VDD
3.0/5.0 V
VL1 = 1/3VSS
VL2 = 2/3VSS
VSS
1/4, 1/3 or 1/2 duty, 1/3 bias
VDD
3.0/5.0 V
VL1 = 1/2VSS
VL2 = 1/2VSS
VSS
1/4, 1/3 or 1/2 duty, 1/2 bias
VL1 and VL2 are
shorted internally.
Note:
Fig. 2.1.1 Configuration of power divider
2.2 Initial Reset
To initialize the S1C60N04 circuits, an initial reset must be executed. There are three ways of doing this.
(1) Initial reset by the power-on reset circuit
(2) External initial reset via the RESET pin
(3) External initial reset by simultaneous high input to pins K00–K03 (depending on mask option)
Figure 2.2.1 shows the configuration of the initial reset circuit.
Vss
RESET
K03
K02
K01
K00
OSC2
OSC1
Oscillation
circuit
Vss
Power-on
reset
circuit
Noise
rejection
circuit
Initial
reset
Noise
rejection
circuit
Fig. 2.2.1 Configuration of initial reset circuit
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相關代理商/技術參數(shù) |
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| S1C60R08 | 制造商:EPSON 制造商全稱:EPSON 功能描述:4-bit Single Chip Microcomputer |
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