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參數(shù)資料
| 型號： | S1C60N04D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC48 |
| 封裝： | DIE-48 |
| 文件頁數(shù)： | 25/50頁 |
| 文件大小： | 372K |
| 代理商： | S1C60N04D |
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S1C60N04 TECHNICAL MANUAL
EPSON
25
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
4.7 Clock Timer
4.7.1 Configuration of clock timer
The S1C60N04 has a built-in clock timer that uses the oscillation circuit as the clock source. The clock
timer is configured as a 7-bit binary counter that counts with a 256 Hz source clock from the divider. The
high-order 4 bits of the counter (16 Hz–2 Hz) can be read by the software.
Figure 4.7.1.1 is the block diagram of the clock timer.
128 Hz–32 Hz
Data bus
32 Hz, 8 Hz, 2 Hz
256 Hz
Clock timer reset signal
Divider
Interrupt
request
Interrupt
control
16 Hz–2 Hz
Oscillation
circuit
Fig. 4.7.1.1 Block diagram of clock timer
Normally, this clock timer is used for all kinds of timing purpose, such as clocks.
4.7.2 Interrupt function
The clock timer can generate interrupts at the falling edge of the 32 Hz, 8 Hz, and 2 Hz signals. The
software can mask any of these interrupt signals.
Figure 4.7.2.1 is the timing chart of the clock timer.
Clock timer timing chart
Frequency
Register
bits
Address
0E4H
D0
16 Hz
D1
D2
D3
8 Hz
4 Hz
2 Hz
Occurrence of
32 Hz interrupt request
Occurrence of
8 Hz interrupt request
Occurrence of
2 Hz interrupt request
Fig. 4.7.2.1 Timing chart of the clock timer
As shown in Figure 4.7.2.1, an interrupt is generated at the falling edge of the 32 Hz, 8 Hz, and 2 Hz
signals. At this point, the corresponding interrupt factor flag (IT32, IT8, IT2) is set to 1. The interrupts can
be masked individually with the interrupt mask register (EIT32, EIT8, EIT2). However, regardless of the
interrupt mask register setting, the interrupt factor flags will be set to 1 at the falling edge of their corre-
sponding signal (e.g. the falling edge of the 2 Hz signal sets the 2 Hz interrupt factor flag to 1).
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