參數(shù)資料
型號： PI7C21P100
廠商： Pericom Semiconductor Corp.
英文描述： 2-PORT PCI-X BRIDGE
中文描述： 2端口PCI - X橋接
文件頁數(shù)： 61/77頁
文件大?。?/td> 603K
代理商： PI7C21P100
PI7C21P100
2-PORT PCI-X BRIDGE
ADVANCE INFORMATION
Page 61 of 77
June 10, 2005 Revision 1.06
8.1.56
SECONDARY BUS UPSTREAM SPLIT TRANSACTION REGISTER –
OFFSET 88h
BIT
FUNCTION
TYPE
DESCRIPTION
31:16
Split Transaction
Commitment Limit
This field indicates the cumulative sequence size of the commitment
limit in units of ADQ’s. Software is allowed to program this field to
any value greater than or equal to the contents of the split transaction
capacity field. For example, if the limit is set to FFFFh, the bridge is
allowed to forward all split requests of any size regardless of the
amount of buffer space available. If the limit is set to 0100h or
greater, causes the bridge to forward accepted split requests of any
size regardless of the amount of buffer space available. The limit can
be programmed at any time after reset. The value of the limit is equal
to the split transaction capacity field reset.
Reset to 0020h
15:0
Split Transaction
Capability
The bridge returns 0020h to indicate that there are 32 ADQ’s (4K
bytes) available buffer space for storing split completions for
memory reads. This applies to requesters on the secondary bus
addressing completers on the primary bus.
Reset to 0020h
RW
Split Transaction Commitment Limit
RO
Split Transaction Capability
8.1.57
PRIMARY BUS DOWNSTREAM SPLIT TRANSACTION REGISTER
– OFFSET 8Ch
BIT
FUNCTION
TYPE
DESCRIPTION
31:16
Split Transaction
Commitment Limit
This field indicates the cumulative sequence size of the commitment
limit in units of ADQ’s. Software is allowed to program this field to
any value greater than or equal to the contents of the split transaction
capacity field. For example, if the limit is set to FFFFh, the bridge is
allowed to forward all split requests of any size regardless of the
amount of buffer space available. If the limit is set to 0100h or
greater, the bridge will forward accepted split requests of any size
regardless of the amount of buffer space available. The limit can be
programmed at any time after reset. The value of the limit is equal to
the split transaction capacity field reset.
Reset to 0020h
15:0
Split Transaction
Capability
The bridge returns 0020h to indicate that there are 32 ADQ’s (4K
bytes) available buffer space for storing split completions for
memory reads. This applies to requesters on the secondary bus
addressing completers on the primary bus.
Reset to 0020h
RW
Split Transaction Commitment Limit
RO
Split Transaction Capability
8.1.58
POWER MANAGEMENT ID REGISTER – OFFSET 90h
BIT
FUNCTION
TYPE
7:0
Power Management ID
RO
DESCRIPTION
Power Management ID
Returns 01h when read indicating that this register set of the
capabilities list is a power management register set.
相關PDF資料
PDF描述
PI7C21P100NH 2-PORT PCI-X BRIDGE
PI7C7100BNA PCI Bus Interface/Controller
PI7C7100 3-Port PCI Bridge
PI7C7100CNA 3-Port PCI Bridge
PI7C7300 3-PORT PCI-to-PCI BRIDGE
相關代理商/技術參數(shù)
參數(shù)描述
PI7C21P100B 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-X TO PCI-X BRIDGE
PI7C21P100BEVB 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C21P100BNH 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-X TO PCI-X BRIDGE
PI7C21P100BNHE 功能描述:外圍驅動器與原件 - PCI PCI-X to PCI-XBridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C21P100EVB 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
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