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參數(shù)資料
| 型號： | PI7C21P100 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-PORT PCI-X BRIDGE |
| 中文描述： | 2端口PCI - X橋接 |
| 文件頁數(shù)： | 11/77頁 |
| 文件大?。?/td> | 603K |
| 代理商： | PI7C21P100 |
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PI7C21P100
2-PORT PCI-X BRIDGE
ADVANCE INFORMATION
Page 11 of 77
June 10, 2005 Revision 1.06
Name
P_TRDY#
Pin #
B15
Type
STS
Description
Primary TRDY (Active LOW).
Driven by the target of
a transaction to indicate its ability to complete current
data phase on the primary side. Once asserted in a data
phase, it is not de-asserted until the end of the data
phase. Before tri-stated, it is driven HIGH for one cycle.
Primary Device Select (Active LOW).
Asserted by the
target indicating that the device is accepting the
transaction. As a master, PI7C21P100 waits for the
assertion of this signal within 5 cycles of P_FRAME#
assertion; otherwise, terminate with master abort. Before
tri-stated, it is driven HIGH for one cycle.
Primary STOP (Active LOW).
Asserted by the target
indicating that the target is requesting the initiator to stop
the current transaction. Before tri-stated, it is driven
HIGH for one cycle.
Primary LOCK (Active LOW).
Asserted by an
initiator, one clock cycle after the first address phase of a
transaction, attempting to perform an operation that may
take more than one PCI transaction to complete.
Primary ID Select.
Used as a chip select line for Type
0 configuration access to PI721P100 configuration
space.
Primary Parity Error (Active LOW).
Asserted when
a data parity error is detected for data received on the
primary interface. Before being tri-stated, it is driven
HIGH for one cycle.
Primary System Error (Active LOW).
Can be driven
LOW by any device to indicate a system error condition.
PI7C21P100 drives this pin on:
Address parity error
Posted write data parity error on target bus
Secondary S_SERR# asserted
Master abort during posted write transaction
Target abort during posted write transaction
Posted write transaction discarded
Delayed write request discarded
Delayed read request discarded
Delayed transaction master timeout
This signal requires an external pull-up resistor for
proper operation.
Primary Request (Active LOW):
This is asserted by
PI7C21P100 to indicate that it wants to start a
transaction on the primary bus. PI7C21P100 de-asserts
this pin for at least 2 PCI clock cycles before asserting it
again.
Primary Grant (Active LOW):
When asserted,
PI7C21P100 can access the primary bus. During idle
and P_GNT# asserted, PI7C21P100 will drive P_AD,
P_CBE, and P_PAR to valid logic levels.
Primary RESET (Active LOW):
When P_RESET# is
active, all PCI signals should be asynchronously tri-
stated.
P_DEVSEL#
D21
STS
P_STOP#
C4
STS
P_LOCK#
C14
I
P_IDSEL
B19
I
P_PERR#
C8
STS
P_SERR#
B4
OD
P_REQ#
B21
TS
P_GNT#
C20
I
P_RST#
E22
I
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C21P100NH | 2-PORT PCI-X BRIDGE |
| PI7C7100BNA | PCI Bus Interface/Controller |
| PI7C7100 | 3-Port PCI Bridge |
| PI7C7100CNA | 3-Port PCI Bridge |
| PI7C7300 | 3-PORT PCI-to-PCI BRIDGE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C21P100B | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-X TO PCI-X BRIDGE |
| PI7C21P100BEVB | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C21P100BNH | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-X TO PCI-X BRIDGE |
| PI7C21P100BNHE | 功能描述:外圍驅(qū)動器與原件 - PCI PCI-X to PCI-XBridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C21P100EVB | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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