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參數(shù)資料
| 型號： | PI7C21P100 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-PORT PCI-X BRIDGE |
| 中文描述： | 2端口PCI - X橋接 |
| 文件頁數(shù)： | 38/77頁 |
| 文件大?。?/td> | 603K |
| 代理商： | PI7C21P100 |
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PI7C21P100
2-PORT PCI-X BRIDGE
ADVANCE INFORMATION
Page 38 of 77
June 10, 2005 Revision 1.06
Table 7-1 DELAY TIMES FOR DE-ASSERTION OF S_RST#
T
PIRSTDLY
Conventional PCI
7 primary clock
cycles
PCI-X 66
6678 primary clock
cycles
100us – 133us
6675 primary clock
cycles
100us – 133us
11 secondary and 7
primary clock
cycles
6687 secondary
clock cycles
100us – 133us
PCI-X 100
13350 primary
clock cycles
133us – 200us
13347 primary
clock cycles
133us – 200us
11 secondary and 7
primary clock
cycles
13350 secondary
clock cycles
133us – 200us
PCI-X 133
13350 primary
clock cycles
100us – 133us
13347 primary
clock cycles
100us – 133us
11 secondary and 7
primary clock
cycles
13350 secondary
clock cycles
100us – 133us
T
XCAP
6675 primary clock
cycles
T
SRSTDLY
11 secondary and 7
primary clock
cycles
16 secondary clock
cycles
T
SIRSTDLY
Note: Primary and secondary clock cycles refer to clock cycles whose period is determined by the P_CLK and
S_CLK inputs.
Table 7-2 DE-ASSERTION OF S_RST#
7.3
BUS PARKING & BUS WIDTH DETERMINATION
Bus parking refers to driving the AD[31:0], CBE[3:0], and PAR lines to a known value while
the bus is idle. In general, the device implementing the bus arbiter is responsible for parking
the bus or assigning another device to park the bus. A device parks the bus when the bus is
idle, its bus grant is asserted, and the device’s request is not asserted. The AD[31:0],
CBE[3:0], and PAR signals are driven LOW after assertion of S_RST#.
PI7C21P100 will assert S_REQ64# for at least 10 PCI clock cycles to allow devices to
determine whether they are connected on a 64-bit bus or 32-bit bus.
7.4
SECONDARY DEVICE MASKING
Secondary devices can be masked through configuration or power strapping of the secondary
bus private device mask register. The process of converting Type 1 configuration transactions
to Type 0 configuration transactions is modified by the contents of the secondary bus private
device mask register. A configuration transaction that targets a device masked by this register
is routed to device 15. Secondary bus architectures which are designed to support masking of
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C21P100NH | 2-PORT PCI-X BRIDGE |
| PI7C7100BNA | PCI Bus Interface/Controller |
| PI7C7100 | 3-Port PCI Bridge |
| PI7C7100CNA | 3-Port PCI Bridge |
| PI7C7300 | 3-PORT PCI-to-PCI BRIDGE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C21P100B | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-X TO PCI-X BRIDGE |
| PI7C21P100BEVB | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C21P100BNH | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-X TO PCI-X BRIDGE |
| PI7C21P100BNHE | 功能描述:外圍驅(qū)動器與原件 - PCI PCI-X to PCI-XBridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C21P100EVB | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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