- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368020 > PI7C21P100 (Pericom Semiconductor Corp.) 2-PORT PCI-X BRIDGE PDF資料下載
參數(shù)資料
| 型號： | PI7C21P100 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 2-PORT PCI-X BRIDGE |
| 中文描述： | 2端口PCI - X橋接 |
| 文件頁數(shù)： | 18/77頁 |
| 文件大?。?/td> | 603K |
| 代理商： | PI7C21P100 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁
PI7C21P100
2-PORT PCI-X BRIDGE
ADVANCE INFORMATION
Page 18 of 77
June 10, 2005 Revision 1.06
3.2.8
TEST SIGNALS
Name
T_DI1
Pin #
Y21
Type
IU
Description
PLL Bypass Control for PCI-X Mode.
The strapped
value of this pin (at P_RST# deassertion) controls
whether the internal PLL’s are bypassed in PCI-X mode.
HIGH: PLL’s are used in PCI-X mode
LOW: PLL’s are bypassed in PCI-X mode
Shorten Initialization Period.
Controls the period for
the following signals during initialization.
LOW: Shorten periods
T
PIRSTDLY
- 5 Primary Clocks
T
XCAP
– 6 Primary Clocks
T
SIRSTDLY
- 40 Secondary Clocks
T
SRSTDLY
– 11 Secondary Clocks + 7 Primary Clocks
HIGH: Normal initialization
T
PIRSTDLY
– See Table 7-2
T
XCAP
– See Table 7-2
T
SIRSTDLY
– See Table 7-2
T
SRSTDLY
– See Table 7-2
PLL Test Control.
Controls along with the internal
PLL testing.
T_RI
T_MODECTL
H
L
H
H
L
H
* P_PLL enabled, S_PLL disabled
**P_PLL disabled, S_PLL enabled
PLL Bypass Control for PCI Mode.
The strapped
value of this pin (at T_RI) controls whether the internal
PLL’s are bypassed in PCI mode.
1: PLL’s are bypassed in PCI mode
0 and T_MODECTL=0: PLL’s are used in PCI mode
Reserved.
Chip testing only. Tie LOW for normal
operation.
T_DI2
AA4
IU
T_MODECTL
T_RI
XCLK_OUT
C1
W22
D3
I
I
I
XCLK_OUT
Z
P_CLK*
S_CLK**
T_RI
W22
I
TEST_CE0
Y23
ID
3.2.9
POWER AND GROUND SIGNALS
Name
P_VDDA
Pin #
A21
Type
P
Description
2.5V Power:
Power supply to the PLL for the primary
clock domain.
2.5V Power:
Ground for the PLL for the primary clock
domain.
2.5V Power:
Power supply to the PLL for the secondary
clock domain.
2.5V Power:
Ground for the PLL for the secondary
clock domain.
2.5 Power:
Power supply for the internal logic
P_VSSA
D16
P
S_VDDA
AB21
P
S_VSSA
Y16
P
VDD
D9, D11, D13, D15,
J4, J20, L4, L20, N4,
N20, R4, R20, Y9,
Y11, Y13, Y15
P
相關PDF資料 |
PDF描述 |
|---|---|
| PI7C21P100NH | 2-PORT PCI-X BRIDGE |
| PI7C7100BNA | PCI Bus Interface/Controller |
| PI7C7100 | 3-Port PCI Bridge |
| PI7C7100CNA | 3-Port PCI Bridge |
| PI7C7300 | 3-PORT PCI-to-PCI BRIDGE |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C21P100B | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-X TO PCI-X BRIDGE |
| PI7C21P100BEVB | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C21P100BNH | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-X TO PCI-X BRIDGE |
| PI7C21P100BNHE | 功能描述:外圍驅(qū)動器與原件 - PCI PCI-X to PCI-XBridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C21P100EVB | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
發(fā)布緊急采購，3分鐘左右您將得到回復。