
PI7C21P100
2-PORT PCI-X BRIDGE
ADVANCE INFORMATION
Page 43 of 77
June 10, 2005 Revision 1.06
BIT
2
FUNCTION
Bus Master Enable
TYPE
RW
DESCRIPTION
Bus Master Control
0:
PI7C21P100 does not initiate memory and I/O transactions on the
primary and disables responses to memory and I/O transactions on
the secondary
1:
Enables PI7C21P100 to operate as a master on the primary for
memory and I/O transactions forwarded from the secondary.
In PCI-X mode, PI7C21P100 is allowed to initiate a split completion
transaction regardless of the status of this bit. Reset to 0
Memory Space Control
0:
Ignore memory transactions on the primary
1:
Enables responses to memory transactions on the primary
Reset to 0
I/O Space Control
0:
Ignores I/O transactions on the primary
1:
Enables responses to I/O transaction on the primary
Reset to 0
1
Memory Space Enable
RW
0
I/O Space Enable
RW
8.1.5
PRIMARY STATUS REGISTER – OFFSET 04h
BIT
FUNCTION
31
Detected Parity Error
TYPE
RWC
DESCRIPTION
Detected Parity Error Status
0:
Address or data parity error not detected by PI7C21P100
1:
Address or data parity error detected by PI7C21P100
Reset to 0
Signaled System Error Status
0:
PI7C21P100 did not assert SERR#
1:
PI7C21P100 asserted SERR#
Reset to 0
Received Master Abort Status
0:
Transaction not terminated with a bus master abort
1:
Transaction terminated with a bus master abort
Reset to 0
Received Target Abort Status
0:
Transaction not terminated with a target abort
1:
Transaction terminated with a target abort
Reset to 0
Signaled Target Abort Status
0:
Target device did not terminate transaction with a target abort
1:
Target device terminated transaction with a target abort
DEVESEL# Timing Status
01:
Medium decoding.
Returns 01h when read.
Data Parity Error Status
0:
No data parity error detected
1:
Data parity error detected
Reset to 0
Fast Back-to-Back Status
0:
Target not capable of decoding fast back-to-back transactions in
PCI-X mode
1:
Target capable of decoding fast back-to-back transactions in
conventional PCI mode
Returns 0 in PCI-X mode and 1 in conventional PCI mode
Reserved.
Returns 0 when read.
66MHz Capable Status
1:
Capable of 66MHz operation
Returns 1 when read.
Capability List
1:
PI7C21P100 supports the capability list and offset 34h is the
pointer to the data structure.
Returns 0 when read.
Reserved.
Returns 0000 when read.
30
Signaled System Error
RWC
29
Received Master Abort
RWC
28
Received Target Abort
RWC
27
Signaled Target Abort
RWC
26:25
DEVSEL# Timing
RO
24
Data Parity Error
RWC
23
Fast Back-to-Back
Capable
RO
22
21
Reserved
66MHz Capable
RO
RO
20
Capability List
RO
19:16
Reserved
RO