參數(shù)資料
型號： PI7C21P100
廠商： Pericom Semiconductor Corp.
英文描述： 2-PORT PCI-X BRIDGE
中文描述： 2端口PCI - X橋接
文件頁數(shù)： 6/77頁
文件大?。?/td> 603K
代理商： PI7C21P100
PI7C21P100
2-PORT PCI-X BRIDGE
ADVANCE INFORMATION
Page 6 of 77
June 10, 2005 Revision 1.06
6.1
6.2
6.3
PRIMARY
AND
SECONDARY
CLOCK
INPUTS................................................................. 34
CLOCK
JITTER........................................................................................................................ 34
MODE
AND
CLOCK
FREQUENCY
DETERMINATION..................................................... 34
PRIMARY BUS..................................................................................................................... 34
SECONDARY BUS............................................................................................................... 35
CLOCK STABILITY.............................................................................................................. 36
DRIVER IMPEDANCE SELECTION................................................................................... 36
RESET............................................................................................................................................... 36
7.1
PRIMARY
INTERFACE
RESET............................................................................................. 37
7.2
SECONDARY
INTERFACE
RESET....................................................................................... 37
7.3
BUS
PARKING
&
BUS
WIDTH
DETERMINATION............................................................. 38
7.4
SECONDARY
DEVICE
MASKING........................................................................................ 38
7.5
ADDRESS
PARITY
ERRORS................................................................................................. 39
7.6
OPTIONAL
BASE
ADDRESS
REGISTER ............................................................................. 39
7.7
OPTIONAL
CONFIGURATION
ACCESS
FROM
THE
SECONDARY
BUS........................ 39
7.8
SHORT
TERM
CACHING....................................................................................................... 40
CONFIGURATION REGISTERS.................................................................................................. 41
8.1
CONFIGURATION
REGISTER
SPACE
MAP........................................................................ 41
8.1.1.1
SIGNAL TYPE DEFINITION................................................................................................... 42
8.1.2
VENDOR ID REGISTER – OFFSET 00h............................................................................. 42
8.1.3
DEVICE ID REGISTER – OFFSET 00h .............................................................................. 42
8.1.4
COMMAND REGISTER – OFFSET 04h.............................................................................. 42
8.1.5
PRIMARY STATUS REGISTER – OFFSET 04h .................................................................. 43
8.1.6
REVISION ID REGISTER – OFFSET 08h........................................................................... 44
8.1.7
CLASS CODE REGISTER – OFFSET 08h........................................................................... 44
8.1.8
CACHE LINE SIZE REGISTER – OFFSET 0Ch ................................................................. 44
8.1.9
PRIMARY LATENCY TIMER – OFFSET 0Ch..................................................................... 44
8.1.10
HEADER TYPE REGISTER – OFFSET 0Ch................................................................... 44
8.1.11
BIST REGISTER – OFFSET 0Ch .................................................................................... 44
8.1.12
LOWER MEMORY BASE ADDRESS REGISTER – OFFSET 10h.................................. 45
8.1.13
UPPER MEMORY BASE ADDRESS REGISTER – OFFSET 14h................................... 45
8.1.14
PRIMARY BUS NUMBER REGISTER – OFFSET 18h................................................... 45
8.1.15
SECONDARY BUS NUMBER REGISTER – OFFSET 18h............................................. 45
8.1.16
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h......................................... 45
8.1.17
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h........................................ 45
8.1.18
I/O BASE ADDRESS REGISTER – OFFSET 1Ch........................................................... 46
8.1.19
I/O LIMIT REGISTER – OFFSET 1Ch............................................................................ 46
8.1.20
SECONDARY STATUS REGISTER – OFFSET 1Ch....................................................... 46
8.1.21
MEMORY BASE REGISTER – OFFSET 20h.................................................................. 47
8.1.22
MEMORY LIMIT REGISTER – OFFSET 20h................................................................. 47
8.1.23
PREFETCHABLE MEMORY BASE REGISTER – OFFSET 24h.................................... 47
8.1.24
PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h................................... 47
8.1.25
PREFETCHABLE BASE UPPER 32-BIT REGISTER – OFFSET 28h............................ 47
8.1.26
PREFETCHABLE LIMIT UPPER 32-BIT REGISTER – OFFSET 2Ch.......................... 48
8.1.27
I/O BASE UPPER 16-BIT REGISTER – OFFSET 30h.................................................... 48
8.1.28
I/O LIMIT UPPER 16-BIT REGISTER – OFFSET 30h .................................................. 48
8.1.29
CAPABILITY POINTER – OFFSET 34h......................................................................... 48
8.1.30
EXPANSION ROM BASE ADDRESS REGISTER – OFFSET 38h.................................. 48
8.1.31
INTERRUPT LINE REGISTER – OFFSET 3Ch.............................................................. 48
8.1.32
INTERRUPT PIN REGISTER – OFFSET 3Ch................................................................ 48
8.1.33
BRIDGE CONTROL REGISTER – OFFSET 3Ch........................................................... 49
8.1.34
PRIMARY DATA BUFFERING CONTROL REGISTER – OFFSET 40h........................ 50
8.1.35
SECONDARY DATA BUFFERING CONTROL REGISTER – OFFSET 40h.................. 51
6.3.1
6.3.2
6.3.3
6.3.4
7
8
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C21P100B 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-X TO PCI-X BRIDGE
PI7C21P100BEVB 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C21P100BNH 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-X TO PCI-X BRIDGE
PI7C21P100BNHE 功能描述:外圍驅(qū)動器與原件 - PCI PCI-X to PCI-XBridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C21P100EVB 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
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