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參數(shù)資料
| 型號： | PDC2 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 8/25頁 |
| 文件大?。?/td> | 291K |
| 代理商： | PDC2 |
8
Peripheral Data Controller 2 (PDC2)
1734B
–
CASIC
–
02/02
Figure 2.
Example of PDC2 Connection with Bridge and SPI
Notes:
1. i = index of peripheral, ranges from 0 to 11, if the SPI is the third peripheral, i = 2.
2. N = the total number of peripherals connected to PDC2. N
s
= the total number of peripherals connected to PDC2 (N)
–
the
number of SPI peripherals. i
S
= index of SPI peripheral, ranges from 0 to (N - N
S
- 1).
3. periph_rx_size= periph_rx_size [(2*i
s
) - 1 + (2N
s
):2*(i
s
-1) + 2*N
s
]
4. periph_tx_size = periph_tx_size [(2*i
s
) - 1 + (2N
s
):2*(i
s
-1) + 2*N
s
]
ba[31:0]
bwrite_from_masters
bwdata[31:0]
bwdata_from_masters[31:0]
master-add[31:0]
bsize[1:0]
bwrite
blok
bprot[1:0]
btran[1:0]
pdc_sel
pdc_size[1:0]
pdc_add[20:0]
pdc_write
periph_rx_rdy[i]
(1)
periph_tx_rdy[i]
(1)
periph_rx_end[i]
(1)
periph_tx_end[i]
(1)
spi_size[1:0]
spi_tx_end
spi_rx_end
spi_tx_rdy
spi_rx_rdy
pdc_data[31:0]
add_master[20:0]
write_master
data_from_master[31:0]
data_to_master[31:0]
pdc_sel
pdc_size[1:0]
pdc_add[20:0]
pdc_write
periph_stb
p_sel_spi[is]
(2)
periph_add[13:0]
periph_write
data_from_periph[31:0]
data_to_periph[31:0]
p_stb_rising
SPI
(spi[is])
(2)
Data from
Memories
PDC2
BRIDGE
Master Signals Manager
periph_select[i]
(2)
periph_stb
periph_write
periph_add[13:0]
pwdata[31:0]
prdata[31:0]
p_d_in[31:0]
periph_add[13:0]
periph_stb
p_d_out[31:0]
p_write
p_sel_spi
p_stb_rising
MUX
ba_from_masters[31:0]
bsize[1:0]
bwrite_from_masters
blok_from_masters
bprot_from_masters[1:0]
btran_from_masters[1:0]
periph_rx_size
(3)
periph_tx_size
(4)
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