參數(shù)資料
型號: PDC2
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 12/25頁
文件大?。?/td> 291K
代理商: PDC2
12
Peripheral Data Controller 2 (PDC2)
1734B
CASIC
02/02
Figure 6.
APB to ASB Transfer with Zero Wait States Following:
1.
2.
Series of APB Accesses Made by Another Master
Memory With One Wait State Made by Another Master
clock
areq (PDC2)
agnt (PDC2)
bridge_sel
agnt (other master)
bwait
bwrite
ba[31:0]
PDC2 status
bwrite (ASB)
ba[31:0] (ASB)
memory_write
pdc_size[1:0]
pdc_write
pdc_add[20:0]
pdc_sel
brdata[31:0]
periph_stb
pstb_rising
periph_add[13:0]
periph_write
data_to_master[31:0]
(output of the bridge)
done
Memory Address
Transfer
NOT GRANTED
NOT GRANTED
Data from Bridge
Peripheral Address
14'h0000
bwrite from Master
done
done
bwrite from Master
Data from Memories
wait
done
wait
wait
done
bwrite from Master
bwrite from Master
Memory Address
ba from Master
ba from Master
ba from Master
Peripheral Address
Data from Bridge
Address from Master
Address from Master
14'h0000
bwrite from Master
Data for Master
Data for PDC Transfer
Data for Master
Locked Idle Cycle
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