3
Peripheral Data Controller 2 (PDC2)
1734B
–
CASIC
–
02/02
Table 1.
PDC2 Pin Description
Name
Definition
Type
Active
Level
Comments
Chip-wide
nreset_r
System Reset
Input
Low
Resets all counters and signals
–
clocked on
rising edge of clock
nreset_f
System Reset
Input
Low
Resets all counters and signals
–
clocked on
falling edge of clock
clock
System Clock
Input
–
System clock
nclock
System Clock
Input
–
Inverted system clock
AMBA System Bus (ASB)
agnt[(asb_n-1):0]
Grant Signal(s)
Input
High
When PDC2 is connected to one ASB, arbiter
grants the bus to the PDC2 when this input is
set to 1.
When PDC2 is connected to two ASBs, bit 0
comes from the arbiter of the ASB dedicated
to internal memories and peripherals; bit 1
comes from the arbiter of the ASB dedicated
to external memories.
bwait[(asb_n-1):0]
Bus Wait(s)
Input
High
When PDC2 is connected to one AST, one
wait cycle is required.
When PDC2 is connected to two ASBs, bit 0
comes from the arbiter of the ASB dedicated
to internal memories and peripherals; bit 1
comes from the arbiter of the ASB dedicated
to external memories.
bridge_sel
Bridge Select
Input
High
From address decoder of system bus
areq[(asb_n-1):0]
Request Signal(s)
Output
High
When PDC2 is connected to one ASB, bus
request is sent to the arbiter.
When PDC2 is connected to two ASBs, bit 0
is sent to the arbiter of the ASB dedicated to
internal memories and peripherals; bit 1 is
sent to the arbiter of the ASB dedicated to
external memories.
oe_master_address
Output Enable
Output
High
Output address enable
–
this signal indicates
that master_add[31:0], blok, bprot[1:0],
bsize[1:0] and bwrite signals are currently
valid with PDC2 granted on the bus
master_add[31:0]
Address System Bus
Output
–
Address bus generated by master
blok
Bus Locked
Output
High
Indicates that the ongoing instruction must
not be interrupted
bprot[1:0]
Bus Protection
Output
–
Protection information
bsize[1:0]
Size of Transfer
Output
–
Bus size