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參數(shù)資料
| 型號： | PDC2 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 4/25頁 |
| 文件大?。?/td> | 291K |
| 代理商： | PDC2 |
4
Peripheral Data Controller 2 (PDC2)
1734B
–
CASIC
–
02/02
btran[(2*asb_n)-1:0]
Type(s) of Transfer
Output
–
Bus transfers.
When PDC2 is connected to two ASBs, LSBs
are reserved for ASB dedicated to internal
memories and peripherals; MSBs are
reserved for ASB dedicated to external
memories.
bwrite
Bus Write
Output
High
The PDC2 transfers data from the peripheral
to internal memory
Dual ASB Mode
remap
Input
High
When high, remap is complete. All memories
are mapped according to the memory map
defined after remap (i.e., internal RAM is now
mapped at address 0x00000000).
When low, remap is not yet complete. The
memory map is as defined prior to remap.
Note: This input is used only when PDC2 is
connected to two AMBA system buses where
one of these is shared by all internal
memories and peripherals and the other
dedicated to external memories.
Any value may be assigned to this pin when
PDC2 is connected to only one ASB.
where_to_boot
Input
When low, indicates that during boot,
operations (before remap) are done on
internal ROM.
When high, indicates that boot memory is an
external memory.
Any value may be assigned to this pin when
PDC2 is connected to only one ASB.
AMBA Peripheral Bus (APB)
periph_write
Peripheral Write Enable
Input
High
From host (Bridge)
periph_stb
Peripheral Strobe
Input
High
From host (Bridge)
periph_add[13:0]
Peripheral Address Bus
Input
–
From host (Bridge)
pwdata[31:0]
Peripheral Data Bus
Input
–
From host (Bridge)
–
user interface data bus
prdata[31:0]
Peripheral Data Bus output
Output
–
User interface data bus
Peripherals
periph_clocks
[per_n-1:0]
Peripheral System Clocks
(UART/ USART/SSC/SPI)
Input
–
Per_n values range from 1 to 12. The number
of each type of peripheral connected to PDC2
is free. For example, the user can have 8
UARTS, 0 USARTS and 3 SPIs. LSBs are
reserved for USARTs. Remaining upper bits
are reserved for SPIs.
periph_rx_rdy
[(per_n-1):0]
Peripheral Receiver Ready
Input
High
Once a character has been received by
peripheral, one of these bits is set to 1.
LSBs are reserved for USARTs. Remaining
upper bits are reserved for SPIs
Table 1.
PDC2 Pin Description (Continued)
Name
Definition
Type
Active
Level
Comments
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| PDC-20-1 | 制造商:MINI 制造商全稱:Mini-Circuits 功能描述:6 to 30 dB COUPLING up to 10W 5 kHz to 2000 MHz |
| PDC-20-1W | 制造商:MINI 制造商全稱:Mini-Circuits 功能描述:6 to 30 dB COUPLING up to 10W 5 kHz to 2000 MHz |
| PDC20275 | 制造商:PROMISE 功能描述: 制造商:Promise Tech 功能描述: |
| PDC20275-E3 | 制造商:Promise Tech 功能描述: |
| PDC-20-3 | 制造商:MINI 制造商全稱:Mini-Circuits 功能描述:6 to 30 dB COUPLING up to 10W 5 kHz to 2000 MHz |
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