參數(shù)資料
型號(hào)： PDC2
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù)： 7/25頁(yè)
文件大小： 291K
代理商： PDC2
7
Peripheral Data Controller 2 (PDC2)
1734B
–
CASIC
–
02/02
If a memory pointer is reprogrammed while the PDC2 is in operation, the transfer addresses
are changed, and the PDC2 performs transfers using the new address.
Transfer
Counters
There is one internal 16-bit transfer counter for each channel. Each counter is used to count
the size of the block already transferred by its associated channel. These counters are decre-
mented after each data transfer. When the counter reaches zero, the transfer is complete and
the PDC2 stops transferring data and disables the trigger while activating the related
periph_end flag if the Next Counter Register is equal to zero.
If the counter is reprogrammed while the PDC2 is operating then the number of transfers is
changed and the PDC2 counts transfers from the new value.
When the Next Counter Register is not equal to zero, for example, the values have been pro-
grammed into Next Pointer/Counter Registers, the behavior is the same, except that, after
activating the flag periph_end when the transfer counter reaches zero, the values of the Next
Pointer/Counter Registers are loaded into the Pointer/Counter Registers in order to re-enable
triggers. The flag periph_end is automatically cleared when one of the counter registers
(Counter or Next Counter Register) is written.
Note:
When the Next Counter Register is loaded into the Counter Register, it is set to zero.
Data Transfers
The peripheral triggers PDC2 transfers using transmit (periph_tx_rdy) and receive
(periph_rx_rdy) signals.
When the peripheral receives an external character, it sends a Receive Ready signal to the
PDC2, which then requests access to the system bus (ASB) from the Bus Arbiter.
When access is granted, the PDC2 starts a read of the peripheral Receive Holding Register,
via the dedicated pdc_add, pdc_sel, pdc_write and pdc_size signals to the Bridge.
Next, the PDC2 triggers a write in the memory by setting the ASB control signals and, at the
same time, the Bridge provides the data that is to be written to the memory.
After each transfer, the relevant PDC2 memory pointer is incremented and the numbers of
transfers left is decremented. When the memory block size is reached, a signal is sent to the
peripheral and the transfer stops.
The same procedure is followed, in reverse, for transmit transfers. These timing exchanges
are shown in the following figures.
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